/*
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* Analogy driver for Sensoray Model 526 board
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*
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* Copyright (C) 2009 Simon Boulay <simon.boulay@gmail.com>
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*
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* Derived from comedi:
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* Copyright (C) 2000 David A. Schleef <ds@schleef.org>
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* 2006 Everett Wang <everett.wang@everteq.com>
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* 2009 Ian Abbott <abbotti@mev.co.uk>
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*
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* This code is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published
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* by the Free Software Foundation; either version 2 of the License,
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* or (at your option) any later version.
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*
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* This code is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Xenomai; if not, write to the Free Software Foundation,
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* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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* Original code comes from comedi linux-next staging driver (2009.12.20)
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* Board documentation: http://www.sensoray.com/products/526data.htm
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* Everything should work as in comedi:
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* - Encoder works
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* - Analog input works
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* - Analog output works
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* - PWM output works
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* - Commands are not supported yet.
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*/
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <asm/byteorder.h>
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#include <rtdm/analogy/device.h>
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/* Board description */
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#define S526_GPCT_CHANS 4
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#define S526_GPCT_BITS 24
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#define S526_AI_CHANS 10 /* 8 regular differential inputs
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* channel 8 is "reference 0" (+10V)
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* channel 9 is "reference 1" (0V) */
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#define S526_AI_BITS 16
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#define S526_AI_TIMEOUT 100
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#define S526_AO_CHANS 4
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#define S526_AO_BITS 16
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#define S526_DIO_CHANS 8
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#define S526_DIO_BITS 1
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/* Ports */
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#define S526_IOSIZE 0x40 /* 64 bytes */
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#define S526_DEFAULT_ADDRESS 0x2C0 /* Manufacturing default */
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/* Registers */
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#define REG_TCR 0x00
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#define REG_WDC 0x02
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#define REG_DAC 0x04
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#define REG_ADC 0x06
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#define REG_ADD 0x08
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#define REG_DIO 0x0A
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#define REG_IER 0x0C
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#define REG_ISR 0x0E
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#define REG_MSC 0x10
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#define REG_C0L 0x12
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#define REG_C0H 0x14
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#define REG_C0M 0x16
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#define REG_C0C 0x18
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#define REG_C1L 0x1A
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#define REG_C1H 0x1C
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#define REG_C1M 0x1E
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#define REG_C1C 0x20
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#define REG_C2L 0x22
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#define REG_C2H 0x24
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#define REG_C2M 0x26
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#define REG_C2C 0x28
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#define REG_C3L 0x2A
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#define REG_C3H 0x2C
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#define REG_C3M 0x2E
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#define REG_C3C 0x30
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#define REG_EED 0x32
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#define REG_EEC 0x34
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#define ISR_ADC_DONE 0x4
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struct counter_mode_register_t {
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#if defined (__LITTLE_ENDIAN_BITFIELD)
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unsigned short coutSource:1;
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unsigned short coutPolarity:1;
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unsigned short autoLoadResetRcap:3;
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unsigned short hwCtEnableSource:2;
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unsigned short ctEnableCtrl:2;
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unsigned short clockSource:2;
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unsigned short countDir:1;
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unsigned short countDirCtrl:1;
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unsigned short outputRegLatchCtrl:1;
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unsigned short preloadRegSel:1;
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unsigned short reserved:1;
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#elif defined(__BIG_ENDIAN_BITFIELD)
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unsigned short reserved:1;
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unsigned short preloadRegSel:1;
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unsigned short outputRegLatchCtrl:1;
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unsigned short countDirCtrl:1;
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unsigned short countDir:1;
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unsigned short clockSource:2;
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unsigned short ctEnableCtrl:2;
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unsigned short hwCtEnableSource:2;
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unsigned short autoLoadResetRcap:3;
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unsigned short coutPolarity:1;
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unsigned short coutSource:1;
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#else
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#error Unknown bit field order
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#endif
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};
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union cmReg {
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struct counter_mode_register_t reg;
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unsigned short value;
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};
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/* Application Classes for GPCT Subdevices */
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enum S526_GPCT_APP_CLASS {
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CountingAndTimeMeasurement,
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SinglePulseGeneration,
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PulseTrainGeneration,
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PositionMeasurement,
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Miscellaneous
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};
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/* GPCT subdevices configuration */
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#define MAX_GPCT_CONFIG_DATA 6
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struct s526GPCTConfig {
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enum S526_GPCT_APP_CLASS app;
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int data[MAX_GPCT_CONFIG_DATA];
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};
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typedef struct s526_priv {
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unsigned long io_base;
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} s526_priv_t;
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struct s526_subd_gpct_priv {
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struct s526GPCTConfig config[4];
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};
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struct s526_subd_ai_priv {
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uint16_t config;
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};
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struct s526_subd_ao_priv {
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uint16_t readback[2];
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};
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struct s526_subd_dio_priv {
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int io_bits;
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unsigned int state;
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};
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#define devpriv ((s526_priv_t*)(dev->priv))
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#define ADDR_REG(reg) (devpriv->io_base + (reg))
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#define ADDR_CHAN_REG(reg, chan) (devpriv->io_base + (reg) + (chan) * 8)
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|
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static int s526_gpct_insn_config(struct a4l_subdevice *subd, struct a4l_kernel_instruction *insn)
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{
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struct a4l_device *dev = subd->dev;
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struct s526_subd_gpct_priv *subdpriv =
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(struct s526_subd_gpct_priv *)subd->priv;
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unsigned int *data = (unsigned int *)insn->data;
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int subdev_channel = CR_CHAN(insn->chan_desc);
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int i;
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short value;
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union cmReg cmReg;
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a4l_dbg(1, drv_dbg, dev,
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"s526_gpct_insn_config: Configuring Channel %d\n",
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subdev_channel);
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for (i = 0; i < MAX_GPCT_CONFIG_DATA; i++) {
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subdpriv->config[subdev_channel].data[i] = data[i];
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a4l_dbg(1, drv_dbg, dev, "data[%d]=%x\n", i, data[i]);
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}
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switch (data[0]) {
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case A4L_INSN_CONFIG_GPCT_QUADRATURE_ENCODER:
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/*
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* data[0]: Application Type
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* data[1]: Counter Mode Register Value
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* data[2]: Pre-load Register Value
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* data[3]: Conter Control Register
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*/
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a4l_dbg(1, drv_dbg, dev, "s526_gpct_insn_config: Configuring Encoder\n");
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subdpriv->config[subdev_channel].app = PositionMeasurement;
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/* Set Counter Mode Register */
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cmReg.value = data[1] & 0xFFFF;
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a4l_dbg(1, drv_dbg, dev, "Counter Mode register=%x\n", cmReg.value);
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outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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/* Reset the counter if it is software preload */
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if (cmReg.reg.autoLoadResetRcap == 0) {
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outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); /* Reset the counter */
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/* outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); /\* Load the counter from PR0 *\/ */
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}
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break;
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case A4L_INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR:
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/*
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* data[0]: Application Type
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* data[1]: Counter Mode Register Value
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* data[2]: Pre-load Register 0 Value
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* data[3]: Pre-load Register 1 Value
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* data[4]: Conter Control Register
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*/
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a4l_dbg(1, drv_dbg, dev, "s526_gpct_insn_config: Configuring SPG\n");
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subdpriv->config[subdev_channel].app = SinglePulseGeneration;
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/* Set Counter Mode Register */
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cmReg.value = (short)(data[1] & 0xFFFF);
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cmReg.reg.preloadRegSel = 0; /* PR0 */
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outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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/* Load the pre-load register 0 high word */
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value = (short)((data[2] >> 16) & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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/* Load the pre-load register 0 low word */
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value = (short)(data[2] & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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/* Set Counter Mode Register */
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cmReg.value = (short)(data[1] & 0xFFFF);
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cmReg.reg.preloadRegSel = 1; /* PR1 */
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outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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/* Load the pre-load register 1 high word */
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value = (short)((data[3] >> 16) & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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/* Load the pre-load register 1 low word */
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value = (short)(data[3] & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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/* Write the Counter Control Register */
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if (data[4] != 0) {
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value = (short)(data[4] & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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}
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break;
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case A4L_INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR:
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/*
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* data[0]: Application Type
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* data[1]: Counter Mode Register Value
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* data[2]: Pre-load Register 0 Value
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* data[3]: Pre-load Register 1 Value
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* data[4]: Conter Control Register
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*/
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a4l_dbg(1, drv_dbg, dev, "s526_gpct_insn_config: Configuring PTG\n");
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subdpriv->config[subdev_channel].app = PulseTrainGeneration;
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/* Set Counter Mode Register */
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cmReg.value = (short)(data[1] & 0xFFFF);
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cmReg.reg.preloadRegSel = 0; /* PR0 */
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outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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/* Load the pre-load register 0 high word */
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value = (short)((data[2] >> 16) & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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/* Load the pre-load register 0 low word */
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value = (short)(data[2] & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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/* Set Counter Mode Register */
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cmReg.value = (short)(data[1] & 0xFFFF);
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cmReg.reg.preloadRegSel = 1; /* PR1 */
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outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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/* Load the pre-load register 1 high word */
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value = (short)((data[3] >> 16) & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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/* Load the pre-load register 1 low word */
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value = (short)(data[3] & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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/* Write the Counter Control Register */
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if (data[4] != 0) {
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value = (short)(data[4] & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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}
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break;
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default:
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a4l_err(dev, "s526_gpct_insn_config: unsupported GPCT_insn_config\n");
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return -EINVAL;
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break;
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}
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return 0;
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}
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static int s526_gpct_rinsn(struct a4l_subdevice *subd, struct a4l_kernel_instruction *insn)
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{
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struct a4l_device *dev = subd->dev;
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uint32_t *data = (uint32_t *)insn->data;
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int counter_channel = CR_CHAN(insn->chan_desc);
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unsigned short datalow;
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unsigned short datahigh;
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int i;
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if (insn->data_size <= 0) {
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a4l_err(dev, "s526_gpct_rinsn: data size should be > 0\n");
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return -EINVAL;
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}
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for (i = 0; i < insn->data_size / sizeof(uint32_t); i++) {
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datalow = inw(ADDR_CHAN_REG(REG_C0L, counter_channel));
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datahigh = inw(ADDR_CHAN_REG(REG_C0H, counter_channel));
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data[i] = (int)(datahigh & 0x00FF);
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data[i] = (data[i] << 16) | (datalow & 0xFFFF);
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a4l_dbg(1, drv_dbg, dev,
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"s526_gpct_rinsn GPCT[%d]: %x(0x%04x, 0x%04x)\n",
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counter_channel, data[i], datahigh, datalow);
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}
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return 0;
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}
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static int s526_gpct_winsn(struct a4l_subdevice *subd, struct a4l_kernel_instruction *insn)
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{
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struct a4l_device *dev = subd->dev;
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struct s526_subd_gpct_priv *subdpriv =
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(struct s526_subd_gpct_priv *)subd->priv;
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uint32_t *data = (uint32_t *)insn->data;
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int subdev_channel = CR_CHAN(insn->chan_desc);
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short value;
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union cmReg cmReg;
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a4l_dbg(1, drv_dbg, dev,
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"s526_gpct_winsn: GPCT_INSN_WRITE on channel %d\n",
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subdev_channel);
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cmReg.value = inw(ADDR_CHAN_REG(REG_C0M, subdev_channel));
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a4l_dbg(1, drv_dbg, dev,
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"s526_gpct_winsn: Counter Mode Register: %x\n", cmReg.value);
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/* Check what Application of Counter this channel is configured for */
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switch (subdpriv->config[subdev_channel].app) {
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case PositionMeasurement:
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a4l_dbg(1, drv_dbg, dev, "s526_gpct_winsn: INSN_WRITE: PM\n");
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outw(0xFFFF & ((*data) >> 16), ADDR_CHAN_REG(REG_C0H,
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subdev_channel));
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outw(0xFFFF & (*data),
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ADDR_CHAN_REG(REG_C0L, subdev_channel));
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break;
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case SinglePulseGeneration:
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a4l_dbg(1, drv_dbg, dev, "s526_gpct_winsn: INSN_WRITE: SPG\n");
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outw(0xFFFF & ((*data) >> 16), ADDR_CHAN_REG(REG_C0H,
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subdev_channel));
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outw(0xFFFF & (*data),
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ADDR_CHAN_REG(REG_C0L, subdev_channel));
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break;
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case PulseTrainGeneration:
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/*
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* data[0] contains the PULSE_WIDTH
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* data[1] contains the PULSE_PERIOD
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* @pre PULSE_PERIOD > PULSE_WIDTH > 0
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* The above periods must be expressed as a multiple of the
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* pulse frequency on the selected source
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*/
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a4l_dbg(1, drv_dbg, dev, "s526_gpct_winsn: INSN_WRITE: PTG\n");
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if ((data[1] > data[0]) && (data[0] > 0)) {
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(subdpriv->config[subdev_channel]).data[0] = data[0];
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(subdpriv->config[subdev_channel]).data[1] = data[1];
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} else {
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a4l_err(dev,
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"s526_gpct_winsn: INSN_WRITE: PTG: Problem with Pulse params -> %du %du\n",
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data[0], data[1]);
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return -EINVAL;
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}
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value = (short)((*data >> 16) & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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value = (short)(*data & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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break;
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default: /* Impossible */
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a4l_err(dev,
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"s526_gpct_winsn: INSN_WRITE: Functionality %d not implemented yet\n",
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subdpriv->config[subdev_channel].app);
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return -EINVAL;
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}
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return 0;
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}
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static int s526_ai_insn_config(struct a4l_subdevice *subd, struct a4l_kernel_instruction *insn)
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{
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struct a4l_device *dev = subd->dev;
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struct s526_subd_ai_priv *subdpriv =
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(struct s526_subd_ai_priv *)subd->priv;
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unsigned int *data = (unsigned int *)insn->data;
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if (insn->data_size < sizeof(unsigned int))
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return -EINVAL;
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/* data[0] : channels was set in relevant bits.
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* data[1] : delay
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*/
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/* COMMENT: abbotti 2008-07-24: I don't know why you'd want to
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* enable channels here. The channel should be enabled in the
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* INSN_READ handler. */
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/* Enable ADC interrupt */
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outw(ISR_ADC_DONE, ADDR_REG(REG_IER));
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a4l_dbg(1, drv_dbg, dev,
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"s526_ai_insn_config: ADC current value: 0x%04x\n",
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inw(ADDR_REG(REG_ADC)));
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subdpriv->config = (data[0] & 0x3FF) << 5;
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if (data[1] > 0)
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subdpriv->config |= 0x8000; /* set the delay */
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subdpriv->config |= 0x0001; /* ADC start bit. */
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return 0;
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}
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static int s526_ai_rinsn(struct a4l_subdevice *subd, struct a4l_kernel_instruction *insn)
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{
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struct a4l_device *dev = subd->dev;
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struct s526_subd_ai_priv *subdpriv =
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(struct s526_subd_ai_priv *)subd->priv;
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uint16_t *data = (uint16_t *)insn->data;
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int n, i;
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int chan = CR_CHAN(insn->chan_desc);
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uint16_t value;
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uint16_t d;
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uint16_t status;
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/* Set configured delay, enable channel for this channel only,
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* select "ADC read" channel, set "ADC start" bit. */
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value = (subdpriv->config & 0x8000) |
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((1 << 5) << chan) | (chan << 1) | 0x0001;
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/* convert n samples */
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for (n = 0; n < insn->data_size / sizeof(uint16_t); n++) {
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/* trigger conversion */
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outw(value, ADDR_REG(REG_ADC));
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a4l_dbg(1, drv_dbg, dev, "s526_ai_rinsn: Wrote 0x%04x to ADC\n",
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value);
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/* wait for conversion to end */
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for (i = 0; i < S526_AI_TIMEOUT; i++) {
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status = inw(ADDR_REG(REG_ISR));
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if (status & ISR_ADC_DONE) {
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outw(ISR_ADC_DONE, ADDR_REG(REG_ISR));
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break;
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}
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}
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if (i == S526_AI_TIMEOUT) {
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a4l_warn(dev, "s526_ai_rinsn: ADC(0x%04x) timeout\n",
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inw(ADDR_REG(REG_ISR)));
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return -ETIMEDOUT;
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}
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/* read data */
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d = inw(ADDR_REG(REG_ADD));
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a4l_dbg(1, drv_dbg, dev, "s526_ai_rinsn: AI[%d]=0x%04x\n",
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n, (uint16_t)(d & 0xFFFF));
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/* munge data */
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data[n] = d ^ 0x8000;
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}
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return 0;
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}
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static int s526_ao_winsn(struct a4l_subdevice *subd, struct a4l_kernel_instruction *insn)
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{
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struct a4l_device *dev = subd->dev;
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struct s526_subd_ao_priv *subdpriv =
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(struct s526_subd_ao_priv *)subd->priv;
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uint16_t *data = (uint16_t *)insn->data;
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int i;
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int chan = CR_CHAN(insn->chan_desc);
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uint16_t val;
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val = chan << 1;
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outw(val, ADDR_REG(REG_DAC));
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for (i = 0; i < insn->data_size / sizeof(uint16_t); i++) {
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outw(data[i], ADDR_REG(REG_ADD)); /* write the data to preload register */
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subdpriv->readback[chan] = data[i];
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outw(val + 1, ADDR_REG(REG_DAC)); /* starts the D/A conversion. */
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}
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return 0;
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}
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static int s526_ao_rinsn(struct a4l_subdevice *subd, struct a4l_kernel_instruction *insn)
|
{
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struct s526_subd_ao_priv *subdpriv =
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(struct s526_subd_ao_priv *)subd->priv;
|
uint16_t *data = (uint16_t *)insn->data;
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int i;
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int chan = CR_CHAN(insn->chan_desc);
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for (i = 0; i < insn->data_size / sizeof(uint16_t); i++)
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data[i] = subdpriv->readback[chan];
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return 0;
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}
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static int s526_dio_insn_config(struct a4l_subdevice *subd, struct a4l_kernel_instruction *insn)
|
{
|
struct a4l_device *dev = subd->dev;
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struct s526_subd_dio_priv *subdpriv =
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(struct s526_subd_dio_priv *)subd->priv;
|
unsigned int *data = (unsigned int *)insn->data;
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int chan = CR_CHAN(insn->chan_desc);
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int group, mask;
|
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group = chan >> 2;
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mask = 0xF << (group << 2);
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|
switch (data[0]) {
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case A4L_INSN_CONFIG_DIO_OUTPUT:
|
subdpriv->state |= 1 << (group + 10); /* bit 10/11 set the
|
* group 1/2's mode */
|
subdpriv->io_bits |= mask;
|
break;
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case A4L_INSN_CONFIG_DIO_INPUT:
|
subdpriv->state &= ~(1 << (group + 10)); /* 1 is output, 0 is
|
* input. */
|
subdpriv->io_bits &= ~mask;
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break;
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case A4L_INSN_CONFIG_DIO_QUERY:
|
data[1] =
|
(subdpriv->io_bits & mask) ? A4L_OUTPUT : A4L_INPUT;
|
return 0;
|
default:
|
return -EINVAL;
|
}
|
|
outw(subdpriv->state, ADDR_REG(REG_DIO));
|
|
return 0;
|
}
|
|
static int s526_dio_insn_bits(struct a4l_subdevice *subd, struct a4l_kernel_instruction *insn)
|
{
|
struct a4l_device *dev = subd->dev;
|
struct s526_subd_dio_priv *subdpriv =
|
(struct s526_subd_dio_priv *)subd->priv;
|
uint8_t *data = (uint8_t *)insn->data;
|
|
if (insn->data_size != 2 * sizeof(uint8_t))
|
return -EINVAL;
|
|
if (data[0]) {
|
subdpriv->state &= ~(data[0]);
|
subdpriv->state |= data[0] & data[1];
|
|
outw(subdpriv->state, ADDR_REG(REG_DIO));
|
}
|
|
data[1] = inw(ADDR_REG(REG_DIO)) & 0xFF; /* low 8 bits are the data */
|
|
return 0;
|
}
|
|
/* --- Channels descriptor --- */
|
|
static struct a4l_channels_desc s526_chan_desc_gpct = {
|
.mode = A4L_CHAN_GLOBAL_CHANDESC,
|
.length = S526_GPCT_CHANS,
|
.chans = {
|
{A4L_CHAN_AREF_GROUND, S526_GPCT_BITS},
|
},
|
};
|
|
static struct a4l_channels_desc s526_chan_desc_ai = {
|
.mode = A4L_CHAN_GLOBAL_CHANDESC,
|
.length = S526_AI_CHANS,
|
.chans = {
|
{A4L_CHAN_AREF_GROUND, S526_AI_BITS},
|
},
|
};
|
|
static struct a4l_channels_desc s526_chan_desc_ao = {
|
.mode = A4L_CHAN_GLOBAL_CHANDESC,
|
.length = S526_AO_CHANS,
|
.chans = {
|
{A4L_CHAN_AREF_GROUND, S526_AO_BITS},
|
},
|
};
|
|
static struct a4l_channels_desc s526_chan_desc_dio = {
|
.mode = A4L_CHAN_GLOBAL_CHANDESC,
|
.length = S526_DIO_CHANS,
|
.chans = {
|
{A4L_CHAN_AREF_GROUND, S526_DIO_BITS},
|
},
|
};
|
|
/* --- Subdevice initialization functions --- */
|
|
/* General purpose counter/timer (gpct) */
|
static void setup_subd_gpct(struct a4l_subdevice *subd)
|
{
|
subd->flags = A4L_SUBD_COUNTER;
|
subd->chan_desc = &s526_chan_desc_gpct;
|
subd->insn_read = s526_gpct_rinsn;
|
subd->insn_config = s526_gpct_insn_config;
|
subd->insn_write = s526_gpct_winsn;
|
}
|
|
/* Analog input subdevice */
|
static void setup_subd_ai(struct a4l_subdevice *subd)
|
{
|
subd->flags = A4L_SUBD_AI;
|
subd->chan_desc = &s526_chan_desc_ai;
|
subd->rng_desc = &a4l_range_bipolar10;
|
subd->insn_read = s526_ai_rinsn;
|
subd->insn_config = s526_ai_insn_config;
|
}
|
|
/* Analog output subdevice */
|
static void setup_subd_ao(struct a4l_subdevice *subd)
|
{
|
subd->flags = A4L_SUBD_AO;
|
subd->chan_desc = &s526_chan_desc_ao;
|
subd->rng_desc = &a4l_range_bipolar10;
|
subd->insn_write = s526_ao_winsn;
|
subd->insn_read = s526_ao_rinsn;
|
}
|
|
/* Digital i/o subdevice */
|
static void setup_subd_dio(struct a4l_subdevice *subd)
|
{
|
subd->flags = A4L_SUBD_DIO;
|
subd->chan_desc = &s526_chan_desc_dio;
|
subd->rng_desc = &range_digital;
|
subd->insn_bits = s526_dio_insn_bits;
|
subd->insn_config = s526_dio_insn_config;
|
}
|
|
struct setup_subd {
|
void (*setup_func) (struct a4l_subdevice *);
|
int sizeof_priv;
|
};
|
|
static struct setup_subd setup_subds[4] = {
|
{
|
.setup_func = setup_subd_gpct,
|
.sizeof_priv = sizeof(struct s526_subd_gpct_priv),
|
},
|
{
|
.setup_func = setup_subd_ai,
|
.sizeof_priv = sizeof(struct s526_subd_ai_priv),
|
},
|
{
|
.setup_func = setup_subd_ao,
|
.sizeof_priv = sizeof(struct s526_subd_ao_priv),
|
},
|
{
|
.setup_func = setup_subd_dio,
|
.sizeof_priv = sizeof(struct s526_subd_dio_priv),
|
},
|
};
|
|
static int dev_s526_attach(struct a4l_device *dev, a4l_lnkdesc_t *arg)
|
{
|
int io_base;
|
int i;
|
int err = 0;
|
|
if (arg->opts == NULL || arg->opts_size < sizeof(unsigned long)) {
|
a4l_warn(dev,
|
"dev_s526_attach: no attach options specified; "
|
"using defaults: addr=0x%x\n",
|
S526_DEFAULT_ADDRESS);
|
io_base = S526_DEFAULT_ADDRESS;
|
} else {
|
io_base = ((unsigned long *)arg->opts)[0];
|
}
|
|
if (!request_region(io_base, S526_IOSIZE, "s526")) {
|
a4l_err(dev, "dev_s526_attach: I/O port conflict\n");
|
return -EIO;
|
}
|
|
/* Allocate the subdevice structures. */
|
for (i = 0; i < 4; i++) {
|
struct a4l_subdevice *subd = a4l_alloc_subd(setup_subds[i].sizeof_priv,
|
setup_subds[i].setup_func);
|
|
if (subd == NULL)
|
return -ENOMEM;
|
|
err = a4l_add_subd(dev, subd);
|
if (err != i)
|
return err;
|
}
|
|
devpriv->io_base = io_base;
|
|
a4l_info(dev, " attached (address = 0x%x)\n", io_base);
|
|
return 0;
|
}
|
|
static int dev_s526_detach(struct a4l_device *dev)
|
{
|
int err = 0;
|
|
if (devpriv->io_base != 0)
|
release_region(devpriv->io_base, S526_IOSIZE);
|
|
return err;
|
}
|
|
static struct a4l_driver drv_s526 = {
|
.owner = THIS_MODULE,
|
.board_name = "analogy_s526",
|
.driver_name = "s526",
|
.attach = dev_s526_attach,
|
.detach = dev_s526_detach,
|
.privdata_size = sizeof(s526_priv_t),
|
};
|
|
static int __init drv_s526_init(void)
|
{
|
return a4l_register_drv(&drv_s526);
|
}
|
|
static void __exit drv_s526_cleanup(void)
|
{
|
a4l_unregister_drv(&drv_s526);
|
}
|
|
MODULE_DESCRIPTION("Analogy driver for Sensoray Model 526 board.");
|
MODULE_LICENSE("GPL");
|
|
module_init(drv_s526_init);
|
module_exit(drv_s526_cleanup);
|
