/*
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* Hardware driver for NI Mite PCI interface chip
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*
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* Copyright (C) 1999 David A. Schleef <ds@schleef.org>
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*
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* This code is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published
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* by the Free Software Foundation; either version 2 of the License,
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* or (at your option) any later version.
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*
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* This code is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Xenomai; if not, write to the Free Software Foundation,
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* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The NI Mite driver was originally written by Tomasz Motylewski
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* <...>, and ported to comedi by ds.
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*
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* References for specifications:
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*
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* 321747b.pdf Register Level Programmer Manual (obsolete)
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* 321747c.pdf Register Level Programmer Manual (new)
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* DAQ-STC reference manual
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*
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* Other possibly relevant info:
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*
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* 320517c.pdf User manual (obsolete)
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* 320517f.pdf User manual (new)
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* 320889a.pdf delete
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* 320906c.pdf maximum signal ratings
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* 321066a.pdf about 16x
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* 321791a.pdf discontinuation of at-mio-16e-10 rev. c
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* 321808a.pdf about at-mio-16e-10 rev P
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* 321837a.pdf discontinuation of at-mio-16de-10 rev d
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* 321838a.pdf about at-mio-16de-10 rev N
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*
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* ISSUES:
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*/
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#include <linux/module.h>
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#include "mite.h"
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#ifdef CONFIG_DEBUG_MITE
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#define MDPRINTK(fmt, args...) rtdm_printk(fmt, ##args)
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#else /* !CONFIG_DEBUG_MITE */
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#define MDPRINTK(fmt, args...)
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#endif /* CONFIG_DEBUG_MITE */
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static LIST_HEAD(mite_devices);
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static struct pci_device_id mite_id[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_NATINST, PCI_ANY_ID), },
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{0, }
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};
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static int mite_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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int i, err = 0;
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struct mite_struct *mite;
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mite = kmalloc(sizeof(struct mite_struct), GFP_KERNEL);
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if(mite == NULL)
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return -ENOMEM;
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memset(mite, 0, sizeof(struct mite_struct));
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rtdm_lock_init(&mite->lock);
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mite->pcidev = dev;
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if (pci_enable_device(dev) < 0) {
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__a4l_err("error enabling mite\n");
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err = -EIO;
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goto out;
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}
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for(i = 0; i < MAX_MITE_DMA_CHANNELS; i++) {
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mite->channels[i].mite = mite;
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mite->channels[i].channel = i;
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mite->channels[i].done = 1;
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}
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list_add(&mite->list, &mite_devices);
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out:
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if (err < 0)
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kfree(mite);
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return err;
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}
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static void mite_remove(struct pci_dev *dev)
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{
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struct list_head *this;
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list_for_each(this, &mite_devices) {
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struct mite_struct *mite =
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list_entry(this, struct mite_struct, list);
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if(mite->pcidev == dev) {
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list_del(this);
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kfree(mite);
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break;
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}
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}
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}
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static struct pci_driver mite_driver = {
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.name = "analogy_mite",
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.id_table = mite_id,
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.probe = mite_probe,
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.remove = mite_remove,
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};
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int a4l_mite_setup(struct mite_struct *mite, int use_iodwbsr_1)
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{
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unsigned long length;
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resource_size_t addr;
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int i;
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u32 csigr_bits;
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unsigned unknown_dma_burst_bits;
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__a4l_dbg(1, drv_dbg, "starting setup...\n");
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pci_set_master(mite->pcidev);
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if (pci_request_regions(mite->pcidev, "mite")) {
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__a4l_err("failed to request mite io regions\n");
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return -EIO;
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};
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/* The PCI BAR0 is the Mite */
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addr = pci_resource_start(mite->pcidev, 0);
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length = pci_resource_len(mite->pcidev, 0);
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mite->mite_phys_addr = addr;
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mite->mite_io_addr = ioremap(addr, length);
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if (!mite->mite_io_addr) {
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__a4l_err("failed to remap mite io memory address\n");
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pci_release_regions(mite->pcidev);
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return -ENOMEM;
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}
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__a4l_dbg(1, drv_dbg, "bar0(mite) 0x%08llx mapped to %p\n",
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(unsigned long long)mite->mite_phys_addr,
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mite->mite_io_addr);
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/* The PCI BAR1 is the DAQ */
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addr = pci_resource_start(mite->pcidev, 1);
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length = pci_resource_len(mite->pcidev, 1);
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mite->daq_phys_addr = addr;
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mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
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if (!mite->daq_io_addr) {
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__a4l_err("failed to remap daq io memory address\n");
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pci_release_regions(mite->pcidev);
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return -ENOMEM;
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}
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__a4l_dbg(1, drv_dbg, "bar0(daq) 0x%08llx mapped to %p\n",
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(unsigned long long)mite->daq_phys_addr,
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mite->daq_io_addr);
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if (use_iodwbsr_1) {
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__a4l_dbg(1, drv_dbg, "using I/O Window Base Size register 1\n");
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writel(0, mite->mite_io_addr + MITE_IODWBSR);
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writel(mite->
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daq_phys_addr | WENAB |
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MITE_IODWBSR_1_WSIZE_bits(length),
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mite->mite_io_addr + MITE_IODWBSR_1);
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writel(0, mite->mite_io_addr + MITE_IODWCR_1);
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} else {
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writel(mite->daq_phys_addr | WENAB,
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mite->mite_io_addr + MITE_IODWBSR);
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}
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/* Make sure dma bursts work. I got this from running a bus analyzer
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on a pxi-6281 and a pxi-6713. 6713 powered up with register value
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of 0x61f and bursts worked. 6281 powered up with register value of
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0x1f and bursts didn't work. The NI windows driver reads the register,
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then does a bitwise-or of 0x600 with it and writes it back.
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*/
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unknown_dma_burst_bits =
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readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
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unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
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writel(unknown_dma_burst_bits,
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mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
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csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
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mite->num_channels = mite_csigr_dmac(csigr_bits);
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if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
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__a4l_err("MITE: bug? chip claims to have %i dma channels. "
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"Setting to %i.\n",
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mite->num_channels, MAX_MITE_DMA_CHANNELS);
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mite->num_channels = MAX_MITE_DMA_CHANNELS;
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}
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__a4l_dbg(1, drv_dbg, " version = %i, type = %i, mite mode = %i, "
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"interface mode = %i\n",
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mite_csigr_version(csigr_bits),
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mite_csigr_type(csigr_bits),
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mite_csigr_mmode(csigr_bits),
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mite_csigr_imode(csigr_bits));
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__a4l_dbg(1, drv_dbg, " num channels = %i, write post fifo depth = %i, "
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"wins = %i, iowins = %i\n",
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mite_csigr_dmac(csigr_bits),
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mite_csigr_wpdep(csigr_bits),
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mite_csigr_wins(csigr_bits),
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mite_csigr_iowins(csigr_bits));
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for (i = 0; i < mite->num_channels; i++) {
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/* Registers the channel as a free one */
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mite->channel_allocated[i] = 0;
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/* Reset the channel */
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writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
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/* Disable interrupts */
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writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
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CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
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CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
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mite->mite_io_addr + MITE_CHCR(i));
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__a4l_dbg(1, drv_dbg, "channel[%d] initialized\n", i);
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}
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mite->used = 1;
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return 0;
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}
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void a4l_mite_unsetup(struct mite_struct *mite)
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{
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if (!mite)
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return;
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if (mite->mite_io_addr) {
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iounmap(mite->mite_io_addr);
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mite->mite_io_addr = NULL;
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}
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if (mite->daq_io_addr) {
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iounmap(mite->daq_io_addr);
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mite->daq_io_addr = NULL;
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}
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if(mite->used)
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pci_release_regions( mite->pcidev );
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mite->used = 0;
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}
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void a4l_mite_list_devices(void)
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{
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struct list_head *this;
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printk("Analogy: MITE: Available NI device IDs:");
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list_for_each(this, &mite_devices) {
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struct mite_struct *mite =
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list_entry(this, struct mite_struct, list);
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printk(" 0x%04x", mite_device_id(mite));
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if(mite->used)
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printk("(used)");
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}
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printk("\n");
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}
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struct mite_struct * a4l_mite_find_device(int bus,
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int slot, unsigned short device_id)
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{
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struct list_head *this;
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list_for_each(this, &mite_devices) {
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struct mite_struct *mite =
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list_entry(this, struct mite_struct, list);
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if(mite->pcidev->device != device_id)
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continue;
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if((bus <= 0 && slot <= 0) ||
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(bus == mite->pcidev->bus->number &&
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slot == PCI_SLOT(mite->pcidev->devfn)))
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return mite;
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}
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return NULL;
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}
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EXPORT_SYMBOL_GPL(a4l_mite_find_device);
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struct mite_channel *
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a4l_mite_request_channel_in_range(struct mite_struct *mite,
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struct mite_dma_descriptor_ring *ring,
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unsigned min_channel, unsigned max_channel)
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{
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int i;
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unsigned long flags;
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struct mite_channel *channel = NULL;
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__a4l_dbg(1, drv_dbg, " min_channel = %u, max_channel = %u\n",
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min_channel, max_channel);
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/* spin lock so a4l_mite_release_channel can be called safely
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from interrupts */
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rtdm_lock_get_irqsave(&mite->lock, flags);
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for (i = min_channel; i <= max_channel; ++i) {
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__a4l_dbg(1, drv_dbg, " channel[%d] allocated = %d\n",
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i, mite->channel_allocated[i]);
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if (mite->channel_allocated[i] == 0) {
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mite->channel_allocated[i] = 1;
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channel = &mite->channels[i];
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channel->ring = ring;
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break;
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}
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}
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rtdm_lock_put_irqrestore(&mite->lock, flags);
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return channel;
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}
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void a4l_mite_release_channel(struct mite_channel *mite_chan)
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{
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struct mite_struct *mite = mite_chan->mite;
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unsigned long flags;
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/* Spin lock to prevent races with mite_request_channel */
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rtdm_lock_get_irqsave(&mite->lock, flags);
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if (mite->channel_allocated[mite_chan->channel]) {
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/* disable all channel's interrupts */
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writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
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CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
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CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
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CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
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mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
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a4l_mite_dma_disarm(mite_chan);
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mite_dma_reset(mite_chan);
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mite->channel_allocated[mite_chan->channel] = 0;
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mite_chan->ring = NULL;
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mmiowb();
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}
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rtdm_lock_put_irqrestore(&mite->lock, flags);
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}
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void a4l_mite_dma_arm(struct mite_channel *mite_chan)
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{
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struct mite_struct *mite = mite_chan->mite;
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int chor;
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unsigned long flags;
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MDPRINTK("a4l_mite_dma_arm ch%i\n", mite_chan->channel);
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/* Memory barrier is intended to insure any twiddling with the buffer
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is done before writing to the mite to arm dma transfer */
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smp_mb();
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/* arm */
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chor = CHOR_START;
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rtdm_lock_get_irqsave(&mite->lock, flags);
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mite_chan->done = 0;
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writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
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mmiowb();
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rtdm_lock_put_irqrestore(&mite->lock, flags);
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}
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void a4l_mite_dma_disarm(struct mite_channel *mite_chan)
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{
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struct mite_struct *mite = mite_chan->mite;
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unsigned chor;
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/* disarm */
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chor = CHOR_ABORT;
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writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
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}
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int a4l_mite_buf_change(struct mite_dma_descriptor_ring *ring, struct a4l_subdevice *subd)
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{
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struct a4l_buffer *buf = subd->buf;
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unsigned int n_links;
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int i;
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if (ring->descriptors) {
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dma_free_coherent(&ring->pcidev->dev,
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ring->n_links * sizeof(struct mite_dma_descriptor),
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ring->descriptors, ring->descriptors_dma_addr);
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}
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ring->descriptors = NULL;
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ring->descriptors_dma_addr = 0;
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ring->n_links = 0;
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if (buf->size == 0) {
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return 0;
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}
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n_links = buf->size >> PAGE_SHIFT;
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MDPRINTK("ring->pcidev=%p, n_links=0x%04x\n", ring->pcidev, n_links);
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ring->descriptors =
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dma_alloc_coherent(&ring->pcidev->dev,
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n_links * sizeof(struct mite_dma_descriptor),
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&ring->descriptors_dma_addr, GFP_ATOMIC);
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if (!ring->descriptors) {
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printk("MITE: ring buffer allocation failed\n");
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return -ENOMEM;
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}
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ring->n_links = n_links;
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for (i = 0; i < n_links; i++) {
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ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
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ring->descriptors[i].addr = cpu_to_le32(buf->pg_list[i]);
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ring->descriptors[i].next =
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cpu_to_le32(ring->descriptors_dma_addr +
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(i + 1) * sizeof(struct mite_dma_descriptor));
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}
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ring->descriptors[n_links - 1].next =
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cpu_to_le32(ring->descriptors_dma_addr);
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/* Barrier is meant to insure that all the writes to the dma descriptors
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have completed before the dma controller is commanded to read them */
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smp_wmb();
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return 0;
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}
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void a4l_mite_prep_dma(struct mite_channel *mite_chan,
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unsigned int num_device_bits, unsigned int num_memory_bits)
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{
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unsigned int chor, chcr, mcr, dcr, lkcr;
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struct mite_struct *mite = mite_chan->mite;
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MDPRINTK("a4l_mite_prep_dma ch%i\n", mite_chan->channel);
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/* reset DMA and FIFO */
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chor = CHOR_DMARESET | CHOR_FRESET;
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writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
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/* short link chaining mode */
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chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
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CHCR_BURSTEN;
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/*
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* Link Complete Interrupt: interrupt every time a link
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* in MITE_RING is completed. This can generate a lot of
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* extra interrupts, but right now we update the values
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* of buf_int_ptr and buf_int_count at each interrupt. A
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* better method is to poll the MITE before each user
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* "read()" to calculate the number of bytes available.
|
*/
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chcr |= CHCR_SET_LC_IE;
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if (num_memory_bits == 32 && num_device_bits == 16) {
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/* Doing a combined 32 and 16 bit byteswap gets the 16
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bit samples into the fifo in the right order.
|
Tested doing 32 bit memory to 16 bit device
|
transfers to the analog out of a pxi-6281, which
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has mite version = 1, type = 4. This also works
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for dma reads from the counters on e-series boards.
|
*/
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chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
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}
|
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if (mite_chan->dir == A4L_INPUT) {
|
chcr |= CHCR_DEV_TO_MEM;
|
}
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writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
|
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/* to/from memory */
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mcr = CR_RL(64) | CR_ASEQUP;
|
switch (num_memory_bits) {
|
case 8:
|
mcr |= CR_PSIZE8;
|
break;
|
case 16:
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mcr |= CR_PSIZE16;
|
break;
|
case 32:
|
mcr |= CR_PSIZE32;
|
break;
|
default:
|
__a4l_err("MITE: bug! "
|
"invalid mem bit width for dma transfer\n");
|
break;
|
}
|
writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
|
|
/* from/to device */
|
dcr = CR_RL(64) | CR_ASEQUP;
|
dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
|
switch (num_device_bits) {
|
case 8:
|
dcr |= CR_PSIZE8;
|
break;
|
case 16:
|
dcr |= CR_PSIZE16;
|
break;
|
case 32:
|
dcr |= CR_PSIZE32;
|
break;
|
default:
|
__a4l_info("MITE: bug! "
|
"invalid dev bit width for dma transfer\n");
|
break;
|
}
|
writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
|
|
/* reset the DAR */
|
writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
|
|
/* the link is 32bits */
|
lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
|
writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
|
|
/* starting address for link chaining */
|
writel(mite_chan->ring->descriptors_dma_addr,
|
mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
|
|
MDPRINTK("exit a4l_mite_prep_dma\n");
|
}
|
|
u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
|
{
|
struct mite_struct *mite = mite_chan->mite;
|
return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
|
}
|
|
u32 a4l_mite_bytes_in_transit(struct mite_channel * mite_chan)
|
{
|
struct mite_struct *mite = mite_chan->mite;
|
return readl(mite->mite_io_addr +
|
MITE_FCR(mite_chan->channel)) & 0x000000FF;
|
}
|
|
/* Returns lower bound for number of bytes transferred from device to memory */
|
u32 a4l_mite_bytes_written_to_memory_lb(struct mite_channel * mite_chan)
|
{
|
u32 device_byte_count;
|
|
device_byte_count = mite_device_bytes_transferred(mite_chan);
|
return device_byte_count - a4l_mite_bytes_in_transit(mite_chan);
|
}
|
|
/* Returns upper bound for number of bytes transferred from device to memory */
|
u32 a4l_mite_bytes_written_to_memory_ub(struct mite_channel * mite_chan)
|
{
|
u32 in_transit_count;
|
|
in_transit_count = a4l_mite_bytes_in_transit(mite_chan);
|
return mite_device_bytes_transferred(mite_chan) - in_transit_count;
|
}
|
|
/* Returns lower bound for number of bytes read from memory for transfer to device */
|
u32 a4l_mite_bytes_read_from_memory_lb(struct mite_channel * mite_chan)
|
{
|
u32 device_byte_count;
|
|
device_byte_count = mite_device_bytes_transferred(mite_chan);
|
return device_byte_count + a4l_mite_bytes_in_transit(mite_chan);
|
}
|
|
/* Returns upper bound for number of bytes read from memory for transfer to device */
|
u32 a4l_mite_bytes_read_from_memory_ub(struct mite_channel * mite_chan)
|
{
|
u32 in_transit_count;
|
|
in_transit_count = a4l_mite_bytes_in_transit(mite_chan);
|
return mite_device_bytes_transferred(mite_chan) + in_transit_count;
|
}
|
|
int a4l_mite_sync_input_dma(struct mite_channel *mite_chan, struct a4l_subdevice *subd)
|
{
|
unsigned int nbytes_lb, nbytes_ub;
|
|
nbytes_lb = a4l_mite_bytes_written_to_memory_lb(mite_chan);
|
nbytes_ub = a4l_mite_bytes_written_to_memory_ub(mite_chan);
|
|
if(a4l_buf_prepare_absput(subd, nbytes_ub) != 0) {
|
__a4l_err("MITE: DMA overwrite of free area\n");
|
return -EPIPE;
|
}
|
|
return a4l_buf_commit_absput(subd, nbytes_lb);
|
}
|
|
int a4l_mite_sync_output_dma(struct mite_channel *mite_chan, struct a4l_subdevice *subd)
|
{
|
struct a4l_buffer *buf = subd->buf;
|
unsigned int nbytes_ub, nbytes_lb;
|
int err;
|
|
nbytes_lb = a4l_mite_bytes_read_from_memory_lb(mite_chan);
|
nbytes_ub = a4l_mite_bytes_read_from_memory_ub(mite_chan);
|
|
err = a4l_buf_prepare_absget(subd, nbytes_ub);
|
if(err < 0) {
|
__a4l_info("MITE: DMA underrun\n");
|
return -EPIPE;
|
}
|
|
err = a4l_buf_commit_absget(subd, nbytes_lb);
|
|
/* If the MITE has already transfered more than required, we
|
can disable it */
|
if (test_bit(A4L_BUF_EOA_NR, &buf->flags))
|
writel(CHOR_STOP,
|
mite_chan->mite->mite_io_addr +
|
MITE_CHOR(mite_chan->channel));
|
|
return err;
|
}
|
|
u32 a4l_mite_get_status(struct mite_channel *mite_chan)
|
{
|
struct mite_struct *mite = mite_chan->mite;
|
u32 status;
|
unsigned long flags;
|
|
rtdm_lock_get_irqsave(&mite->lock, flags);
|
status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
|
if (status & CHSR_DONE) {
|
mite_chan->done = 1;
|
writel(CHOR_CLRDONE,
|
mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
|
}
|
mmiowb();
|
rtdm_lock_put_irqrestore(&mite->lock, flags);
|
return status;
|
}
|
|
int a4l_mite_done(struct mite_channel *mite_chan)
|
{
|
struct mite_struct *mite = mite_chan->mite;
|
unsigned long flags;
|
int done;
|
|
a4l_mite_get_status(mite_chan);
|
rtdm_lock_get_irqsave(&mite->lock, flags);
|
done = mite_chan->done;
|
rtdm_lock_put_irqrestore(&mite->lock, flags);
|
return done;
|
}
|
|
#ifdef CONFIG_DEBUG_MITE
|
|
static void a4l_mite_decode(const char *const bit_str[], unsigned int bits);
|
|
/* names of bits in mite registers */
|
|
static const char *const mite_CHOR_strings[] = {
|
"start", "cont", "stop", "abort",
|
"freset", "clrlc", "clrrb", "clrdone",
|
"clr_lpause", "set_lpause", "clr_send_tc",
|
"set_send_tc", "12", "13", "14",
|
"15", "16", "17", "18",
|
"19", "20", "21", "22",
|
"23", "24", "25", "26",
|
"27", "28", "29", "30",
|
"dmareset",
|
};
|
|
static const char *const mite_CHCR_strings[] = {
|
"continue", "ringbuff", "2", "3",
|
"4", "5", "6", "7",
|
"8", "9", "10", "11",
|
"12", "13", "bursten", "fifodis",
|
"clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
|
"clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
|
"clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
|
"clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
|
};
|
|
static const char *const mite_MCR_strings[] = {
|
"amdevice", "1", "2", "3",
|
"4", "5", "portio", "portvxi",
|
"psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
|
"12", "13", "blocken", "berhand",
|
"reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
|
"rd512", "rl1", "rl2", "rl8",
|
"24", "25", "26", "27",
|
"28", "29", "30", "stopen",
|
};
|
|
static const char *const mite_DCR_strings[] = {
|
"amdevice", "1", "2", "3",
|
"4", "5", "portio", "portvxi",
|
"psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
|
"aseqxp8", "13", "blocken", "berhand",
|
"reqsintlim", "reqs1", "reqs2", "rd32",
|
"rd512", "rl1", "rl2", "rl8",
|
"23", "24", "25", "27",
|
"28", "wsdevc", "wsdevs", "rwdevpack",
|
};
|
|
static const char *const mite_LKCR_strings[] = {
|
"amdevice", "1", "2", "3",
|
"4", "5", "portio", "portvxi",
|
"psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
|
"12", "13", "14", "berhand",
|
"16", "17", "18", "rd32",
|
"rd512", "rl1", "rl2", "rl8",
|
"24", "25", "26", "27",
|
"28", "29", "30", "chngend",
|
};
|
|
static const char *const mite_CHSR_strings[] = {
|
"d.err0", "d.err1", "m.err0", "m.err1",
|
"l.err0", "l.err1", "drq0", "drq1",
|
"end", "xferr", "operr0", "operr1",
|
"stops", "habort", "sabort", "error",
|
"16", "conts_rb", "18", "linkc",
|
"20", "drdy", "22", "mrdy",
|
"24", "done", "26", "sars",
|
"28", "lpauses", "30", "int",
|
};
|
|
void a4l_mite_dump_regs(struct mite_channel *mite_chan)
|
{
|
unsigned long mite_io_addr =
|
(unsigned long)mite_chan->mite->mite_io_addr;
|
unsigned long addr = 0;
|
unsigned long temp = 0;
|
|
printk("a4l_mite_dump_regs ch%i\n", mite_chan->channel);
|
printk("mite address is =0x%08lx\n", mite_io_addr);
|
|
addr = mite_io_addr + MITE_CHOR(mite_chan->channel);
|
printk("mite status[CHOR]at 0x%08lx =0x%08lx\n", addr, temp =
|
readl((void *)addr));
|
a4l_mite_decode(mite_CHOR_strings, temp);
|
addr = mite_io_addr + MITE_CHCR(mite_chan->channel);
|
printk("mite status[CHCR]at 0x%08lx =0x%08lx\n", addr, temp =
|
readl((void *)addr));
|
a4l_mite_decode(mite_CHCR_strings, temp);
|
addr = mite_io_addr + MITE_TCR(mite_chan->channel);
|
printk("mite status[TCR] at 0x%08lx =0x%08x\n", addr,
|
readl((void *)addr));
|
addr = mite_io_addr + MITE_MCR(mite_chan->channel);
|
printk("mite status[MCR] at 0x%08lx =0x%08lx\n", addr, temp =
|
readl((void *)addr));
|
a4l_mite_decode(mite_MCR_strings, temp);
|
|
addr = mite_io_addr + MITE_MAR(mite_chan->channel);
|
printk("mite status[MAR] at 0x%08lx =0x%08x\n", addr,
|
readl((void *)addr));
|
addr = mite_io_addr + MITE_DCR(mite_chan->channel);
|
printk("mite status[DCR] at 0x%08lx =0x%08lx\n", addr, temp =
|
readl((void *)addr));
|
a4l_mite_decode(mite_DCR_strings, temp);
|
addr = mite_io_addr + MITE_DAR(mite_chan->channel);
|
printk("mite status[DAR] at 0x%08lx =0x%08x\n", addr,
|
readl((void *)addr));
|
addr = mite_io_addr + MITE_LKCR(mite_chan->channel);
|
printk("mite status[LKCR]at 0x%08lx =0x%08lx\n", addr, temp =
|
readl((void *)addr));
|
a4l_mite_decode(mite_LKCR_strings, temp);
|
addr = mite_io_addr + MITE_LKAR(mite_chan->channel);
|
printk("mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
|
readl((void *)addr));
|
|
addr = mite_io_addr + MITE_CHSR(mite_chan->channel);
|
printk("mite status[CHSR]at 0x%08lx =0x%08lx\n", addr, temp =
|
readl((void *)addr));
|
a4l_mite_decode(mite_CHSR_strings, temp);
|
addr = mite_io_addr + MITE_FCR(mite_chan->channel);
|
printk("mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
|
readl((void *)addr));
|
}
|
|
|
static void a4l_mite_decode(const char *const bit_str[], unsigned int bits)
|
{
|
int i;
|
|
for (i = 31; i >= 0; i--) {
|
if (bits & (1 << i)) {
|
printk(" %s", bit_str[i]);
|
}
|
}
|
printk("\n");
|
}
|
|
#endif /* CONFIG_DEBUG_MITE */
|
|
|
static int __init mite_init(void)
|
{
|
int err;
|
|
/* Register the mite's PCI driver */
|
err = pci_register_driver(&mite_driver);
|
|
if(err == 0)
|
a4l_mite_list_devices();
|
|
return err;
|
}
|
|
static void __exit mite_cleanup(void)
|
{
|
|
/* Unregister the PCI structure driver */
|
pci_unregister_driver(&mite_driver);
|
|
/* Just paranoia... */
|
while(&mite_devices != mite_devices.next) {
|
struct list_head *this = mite_devices.next;
|
struct mite_struct *mite =
|
list_entry(this, struct mite_struct, list);
|
|
list_del(this);
|
kfree(mite);
|
}
|
}
|
|
MODULE_LICENSE("GPL");
|
module_init(mite_init);
|
module_exit(mite_cleanup);
|
|
EXPORT_SYMBOL_GPL(a4l_mite_dma_arm);
|
EXPORT_SYMBOL_GPL(a4l_mite_dma_disarm);
|
EXPORT_SYMBOL_GPL(a4l_mite_sync_input_dma);
|
EXPORT_SYMBOL_GPL(a4l_mite_sync_output_dma);
|
EXPORT_SYMBOL_GPL(a4l_mite_setup);
|
EXPORT_SYMBOL_GPL(a4l_mite_unsetup);
|
EXPORT_SYMBOL_GPL(a4l_mite_list_devices);
|
EXPORT_SYMBOL_GPL(a4l_mite_request_channel_in_range);
|
EXPORT_SYMBOL_GPL(a4l_mite_release_channel);
|
EXPORT_SYMBOL_GPL(a4l_mite_prep_dma);
|
EXPORT_SYMBOL_GPL(a4l_mite_buf_change);
|
EXPORT_SYMBOL_GPL(a4l_mite_bytes_written_to_memory_lb);
|
EXPORT_SYMBOL_GPL(a4l_mite_bytes_written_to_memory_ub);
|
EXPORT_SYMBOL_GPL(a4l_mite_bytes_read_from_memory_lb);
|
EXPORT_SYMBOL_GPL(a4l_mite_bytes_read_from_memory_ub);
|
EXPORT_SYMBOL_GPL(a4l_mite_bytes_in_transit);
|
EXPORT_SYMBOL_GPL(a4l_mite_get_status);
|
EXPORT_SYMBOL_GPL(a4l_mite_done);
|
#ifdef CONFIG_DEBUG_MITE
|
EXPORT_SYMBOL_GPL(a4l_mite_decode);
|
EXPORT_SYMBOL_GPL(a4l_mite_dump_regs);
|
#endif /* CONFIG_DEBUG_MITE */
|
