/*
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* Copyright (C) 2001-2013 Philippe Gerum <rpm@xenomai.org>.
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* Copyright (C) 2004-2006 Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>.
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*
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* Xenomai is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Xenomai is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Xenomai; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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* 02111-1307, USA.
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*/
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#ifndef _COBALT_X86_ASM_THREAD_H
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#define _COBALT_X86_ASM_THREAD_H
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#include <asm-generic/xenomai/ipipe/thread.h>
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#include <asm/xenomai/wrappers.h>
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#include <asm/traps.h>
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#ifndef IPIPE_X86_FPU_EAGER
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0)
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typedef union thread_xstate x86_fpustate;
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#define x86_fpustate_ptr(t) ((t)->fpu.state)
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#else
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typedef union fpregs_state x86_fpustate;
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#define x86_fpustate_ptr(t) ((t)->fpu.active_state)
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#endif
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#endif
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struct xnarchtcb {
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struct xntcb core;
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0)
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unsigned long sp;
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unsigned long *spp;
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unsigned long ip;
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unsigned long *ipp;
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#endif
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#ifdef IPIPE_X86_FPU_EAGER
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struct fpu *kfpu;
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#else
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x86_fpustate *fpup;
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unsigned int root_used_math: 1;
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x86_fpustate *kfpu_state;
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#endif
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unsigned int root_kfpu: 1;
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};
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#define xnarch_fpu_ptr(tcb) ((tcb)->fpup)
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#define xnarch_fault_regs(d) ((d)->regs)
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#define xnarch_fault_trap(d) ((d)->exception)
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#define xnarch_fault_code(d) ((d)->regs->orig_ax)
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#define xnarch_fault_pc(d) ((d)->regs->ip)
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#define xnarch_fault_fpu_p(d) ((d)->exception == X86_TRAP_NM)
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#define xnarch_fault_pf_p(d) ((d)->exception == X86_TRAP_PF)
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#define xnarch_fault_bp_p(d) ((current->ptrace & PT_PTRACED) && \
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((d)->exception == X86_TRAP_DB || (d)->exception == X86_TRAP_BP))
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#define xnarch_fault_notify(d) (!xnarch_fault_bp_p(d))
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static inline
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struct task_struct *xnarch_host_task(struct xnarchtcb *tcb)
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{
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return tcb->core.host_task;
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}
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void xnarch_switch_fpu(struct xnthread *from, struct xnthread *to);
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int xnarch_handle_fpu_fault(struct xnthread *from,
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struct xnthread *to, struct ipipe_trap_data *d);
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void xnarch_leave_root(struct xnthread *root);
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void xnarch_init_root_tcb(struct xnthread *thread);
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void xnarch_init_shadow_tcb(struct xnthread *thread);
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void xnarch_switch_to(struct xnthread *out, struct xnthread *in);
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static inline void xnarch_enter_root(struct xnthread *root) { }
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static inline int xnarch_escalate(void)
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{
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if (ipipe_root_p) {
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ipipe_raise_irq(cobalt_pipeline.escalate_virq);
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return 1;
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}
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return 0;
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}
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int mach_x86_thread_init(void);
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void mach_x86_thread_cleanup(void);
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#endif /* !_COBALT_X86_ASM_THREAD_H */
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