/*
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* Copyright (C) 2008 Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*/
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#ifndef _COBALT_ARM_ASM_UAPI_ARITH_H
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#define _COBALT_ARM_ASM_UAPI_ARITH_H
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#include <asm/xenomai/uapi/features.h>
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#if __LINUX_ARM_ARCH__ >= 4 && (!defined(CONFIG_THUMB2_KERNEL) || !defined(CONFIG_FTRACE))
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static inline __attribute__((__const__)) unsigned long long
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mach_arm_nodiv_ullimd(const unsigned long long op,
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const unsigned long long frac,
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const unsigned rhs_integ);
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#define xnarch_nodiv_ullimd(op, frac, integ) \
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mach_arm_nodiv_ullimd((op), (frac), (integ))
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static inline __attribute__((__const__)) long long
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mach_arm_nodiv_llimd(const long long op,
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const unsigned long long frac,
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const unsigned rhs_integ);
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#define xnarch_nodiv_llimd(op, frac, integ) \
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mach_arm_nodiv_llimd((op), (frac), (integ))
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#else /* arm <= v3 */
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#define xnarch_add96and64(l0, l1, l2, s0, s1) \
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do { \
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__asm__ ("adds %2, %2, %4\n\t" \
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"adcs %1, %1, %3\n\t" \
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"adc %0, %0, #0\n\t" \
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: "+r"(l0), "+r"(l1), "+r"(l2) \
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: "r"(s0), "r"(s1): "cc"); \
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} while (0)
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#endif /* arm <= v3 */
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#include <cobalt/uapi/asm-generic/arith.h>
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#if __LINUX_ARM_ARCH__ >= 4 && (!defined(CONFIG_THUMB2_KERNEL) || !defined(CONFIG_FTRACE))
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#define mach_arm_nodiv_ullimd_str \
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"umull %[tl], %[rl], %[opl], %[fracl]\n\t" \
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"umull %[rm], %[rh], %[oph], %[frach]\n\t" \
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"adds %[rl], %[rl], %[tl], lsr #31\n\t" \
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"adcs %[rm], %[rm], #0\n\t" \
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"adc %[rh], %[rh], #0\n\t" \
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"umull %[tl], %[th], %[oph], %[fracl]\n\t" \
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"adds %[rl], %[rl], %[tl]\n\t" \
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"adcs %[rm], %[rm], %[th]\n\t" \
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"adc %[rh], %[rh], #0\n\t" \
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"umull %[tl], %[th], %[opl], %[frach]\n\t" \
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"adds %[rl], %[rl], %[tl]\n\t" \
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"adcs %[rm], %[rm], %[th]\n\t" \
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"adc %[rh], %[rh], #0\n\t" \
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"umlal %[rm], %[rh], %[opl], %[integ]\n\t" \
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"mla %[rh], %[oph], %[integ], %[rh]\n\t"
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static inline __attribute__((__const__)) unsigned long long
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mach_arm_nodiv_ullimd(const unsigned long long op,
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const unsigned long long frac,
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const unsigned rhs_integ)
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{
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register unsigned rl __asm__("r5");
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register unsigned rm __asm__("r0");
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register unsigned rh __asm__("r1");
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register unsigned fracl __asm__ ("r2");
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register unsigned frach __asm__ ("r3");
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register unsigned integ __asm__("r4") = rhs_integ;
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register unsigned opl __asm__ ("r6");
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register unsigned oph __asm__ ("r8");
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register unsigned tl __asm__("r9");
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register unsigned th __asm__("r10");
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xnarch_u64tou32(op, oph, opl);
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xnarch_u64tou32(frac, frach, fracl);
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__asm__ (mach_arm_nodiv_ullimd_str
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: [rl]"=r"(rl), [rm]"=r"(rm), [rh]"=r"(rh),
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[tl]"=r"(tl), [th]"=r"(th)
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: [opl]"r"(opl), [oph]"r"(oph),
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[fracl]"r"(fracl), [frach]"r"(frach),
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[integ]"r"(integ)
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: "cc");
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return xnarch_u64fromu32(rh, rm);
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}
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static inline __attribute__((__const__)) long long
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mach_arm_nodiv_llimd(const long long op,
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const unsigned long long frac,
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const unsigned rhs_integ)
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{
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register unsigned rl __asm__("r5");
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register unsigned rm __asm__("r0");
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register unsigned rh __asm__("r1");
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register unsigned fracl __asm__ ("r2");
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register unsigned frach __asm__ ("r3");
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register unsigned integ __asm__("r4") = rhs_integ;
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register unsigned opl __asm__ ("r6");
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register unsigned oph __asm__ ("r8");
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register unsigned tl __asm__("r9");
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register unsigned th __asm__("r10");
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register unsigned s __asm__("r12");
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xnarch_u64tou32(op, oph, opl);
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xnarch_u64tou32(frac, frach, fracl);
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__asm__ ("movs %[s], %[oph], lsr #30\n\t"
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"beq 1f\n\t"
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"rsbs %[opl], %[opl], #0\n\t"
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"sbc %[oph], %[oph], %[oph], lsl #1\n"
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"1:\t"
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mach_arm_nodiv_ullimd_str
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"teq %[s], #0\n\t"
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"beq 2f\n\t"
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"rsbs %[rm], %[rm], #0\n\t"
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"sbc %[rh], %[rh], %[rh], lsl #1\n"
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"2:\t"
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: [rl]"=r"(rl), [rm]"=r"(rm), [rh]"=r"(rh),
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[tl]"=r"(tl), [th]"=r"(th), [s]"=r"(s)
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: [opl]"r"(opl), [oph]"r"(oph),
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[fracl]"r"(fracl), [frach]"r"(frach),
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[integ]"r"(integ)
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: "cc");
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return xnarch_u64fromu32(rh, rm);
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}
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#endif /* arm >= v4 */
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#endif /* _COBALT_ARM_ASM_UAPI_ARITH_H */
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