/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* linux/mdio.h: definitions for MDIO (clause 45) transceivers
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* Copyright 2006-2009 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef _UAPI__LINUX_MDIO_H__
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#define _UAPI__LINUX_MDIO_H__
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#include <linux/types.h>
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#include <linux/mii.h>
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/* MDIO Manageable Devices (MMDs). */
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#define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/
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* Physical Medium Dependent */
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#define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */
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#define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */
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#define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
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#define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
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#define MDIO_MMD_TC 6 /* Transmission Convergence */
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#define MDIO_MMD_AN 7 /* Auto-Negotiation */
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#define MDIO_MMD_C22EXT 29 /* Clause 22 extension */
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#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */
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#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */
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/* Generic MDIO registers. */
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#define MDIO_CTRL1 MII_BMCR
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#define MDIO_STAT1 MII_BMSR
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#define MDIO_DEVID1 MII_PHYSID1
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#define MDIO_DEVID2 MII_PHYSID2
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#define MDIO_SPEED 4 /* Speed ability */
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#define MDIO_DEVS1 5 /* Devices in package */
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#define MDIO_DEVS2 6
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#define MDIO_CTRL2 7 /* 10G control 2 */
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#define MDIO_STAT2 8 /* 10G status 2 */
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#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
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#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
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#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
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#define MDIO_PKGID1 14 /* Package identifier */
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#define MDIO_PKGID2 15
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#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
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#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
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#define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */
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#define MDIO_PCS_EEE_ABLE2 21 /* EEE Capability register 2 */
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#define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
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#define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */
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#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
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#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
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#define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */
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#define MDIO_AN_EEE_ADV2 62 /* EEE advertisement 2 */
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#define MDIO_AN_EEE_LPABLE2 63 /* EEE link partner ability 2 */
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/* Media-dependent registers. */
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#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
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#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
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#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
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* Lanes B-D are numbered 134-136. */
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#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
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#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
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#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
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#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
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#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
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#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
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/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
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#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
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#define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
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#define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
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#define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
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#define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
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#define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
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/* Control register 1. */
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/* Enable extended speed selection */
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#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)
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/* All speed selection bits */
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#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
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#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
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#define MDIO_CTRL1_LPOWER BMCR_PDOWN
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#define MDIO_CTRL1_RESET BMCR_RESET
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#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
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#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
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#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
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#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
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#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
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#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
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#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
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#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
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#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */
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/* 10 Gb/s */
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#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
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/* 10PASS-TS/2BASE-TL */
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#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04)
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/* 2.5 Gb/s */
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#define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18)
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/* 5 Gb/s */
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#define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c)
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/* Status register 1. */
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#define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */
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#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
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#define MDIO_STAT1_FAULT 0x0080 /* Fault */
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#define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */
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#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE
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#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT
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#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE
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#define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */
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#define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */
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/* Speed register. */
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#define MDIO_SPEED_10G 0x0001 /* 10G capable */
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#define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
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#define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
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#define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */
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#define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */
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#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */
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#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
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/* Device present registers. */
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#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
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#define MDIO_DEVS_C22PRESENT MDIO_DEVS_PRESENT(0)
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#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
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#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
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#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
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#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
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#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
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#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC)
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#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
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#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
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#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
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#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
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/* Control register 2. */
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#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */
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#define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
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#define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */
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#define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */
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#define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */
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#define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */
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#define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */
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#define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */
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#define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */
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#define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */
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#define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */
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#define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */
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#define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */
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#define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */
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#define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */
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#define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */
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#define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
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#define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */
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#define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */
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#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */
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#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
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#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
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#define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */
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#define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */
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/* Status register 2. */
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#define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */
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#define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */
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#define MDIO_STAT2_DEVPRST 0xc000 /* Device present */
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#define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */
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#define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */
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#define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */
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#define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */
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#define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */
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#define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */
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#define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */
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#define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */
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#define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */
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#define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */
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#define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */
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#define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
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#define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
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#define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */
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#define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */
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#define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */
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#define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
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#define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
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/* Transmit disable register. */
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#define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */
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#define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */
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#define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */
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#define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */
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#define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */
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/* Receive signal detect register. */
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#define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */
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#define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */
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#define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */
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#define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */
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#define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */
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/* Extended abilities register. */
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#define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */
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#define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */
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#define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */
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#define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */
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#define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */
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#define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */
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#define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
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#define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
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#define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
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#define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */
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/* PHY XGXS lane state register. */
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#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
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#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002
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#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004
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#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008
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#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000
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/* PMA 10GBASE-T pair swap & polarity */
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#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */
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#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */
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#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */
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#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */
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#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */
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#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */
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/* PMA 10GBASE-T TX power register. */
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#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */
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/* PMA 10GBASE-T SNR registers. */
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/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
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#define MDIO_PMA_10GBT_SNR_BIAS 0x8000
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#define MDIO_PMA_10GBT_SNR_MAX 127
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/* PMA 10GBASE-R FEC ability register. */
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#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */
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#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */
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/* PCS 10GBASE-R/-T status register 1. */
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#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */
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/* PCS 10GBASE-R/-T status register 2. */
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#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff
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#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00
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/* AN 10GBASE-T control register. */
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#define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */
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#define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */
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#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */
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/* AN 10GBASE-T status register. */
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#define MDIO_AN_10GBT_STAT_LP2_5G 0x0020 /* LP is 2.5GBT capable */
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#define MDIO_AN_10GBT_STAT_LP5G 0x0040 /* LP is 5GBT capable */
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#define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */
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#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */
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#define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */
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#define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */
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#define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */
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#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
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#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
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/* EEE Supported/Advertisement/LP Advertisement registers.
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*
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* EEE capability Register (3.20), Advertisement (7.60) and
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* Link partner ability (7.61) registers have and can use the same identical
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* bit masks.
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*/
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#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
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#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */
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/* Note: the two defines above can be potentially used by the user-land
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* and cannot remove them now.
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* So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros
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* using the previous ones (that can be considered obsolete).
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*/
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#define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */
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#define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T /* 1000T EEE cap */
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#define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */
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#define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */
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#define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */
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#define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */
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#define MDIO_EEE_40GR_FW 0x0100 /* 40G R fast wake */
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#define MDIO_EEE_40GR_DS 0x0200 /* 40G R deep sleep */
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#define MDIO_EEE_100GR_FW 0x1000 /* 100G R fast wake */
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#define MDIO_EEE_100GR_DS 0x2000 /* 100G R deep sleep */
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#define MDIO_EEE_2_5GT 0x0001 /* 2.5GT EEE cap */
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#define MDIO_EEE_5GT 0x0002 /* 5GT EEE cap */
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/* 2.5G/5G Extended abilities register. */
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#define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 /* 2.5GBASET ability */
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#define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 /* 5GBASET ability */
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/* LASI RX_ALARM control/status registers. */
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#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
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#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */
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#define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */
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#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */
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#define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */
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/* LASI TX_ALARM control/status registers. */
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#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */
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#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */
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#define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */
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#define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */
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#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */
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#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */
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/* LASI control/status registers. */
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#define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */
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#define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */
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#define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */
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/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
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#define MDIO_PHY_ID_C45 0x8000
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#define MDIO_PHY_ID_PRTAD 0x03e0
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#define MDIO_PHY_ID_DEVAD 0x001f
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#define MDIO_PHY_ID_C45_MASK \
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(MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
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static inline __u16 mdio_phy_id_c45(int prtad, int devad)
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{
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return MDIO_PHY_ID_C45 | (prtad << 5) | devad;
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}
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/* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/
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#define MDIO_USXGMII_EEE_CLK_STP 0x0080 /* EEE clock stop supported */
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#define MDIO_USXGMII_EEE 0x0100 /* EEE supported */
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#define MDIO_USXGMII_SPD_MASK 0x0e00 /* USXGMII speed mask */
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#define MDIO_USXGMII_FULL_DUPLEX 0x1000 /* USXGMII full duplex */
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#define MDIO_USXGMII_DPX_SPD_MASK 0x1e00 /* USXGMII duplex and speed bits */
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#define MDIO_USXGMII_10 0x0000 /* 10Mbps */
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#define MDIO_USXGMII_10HALF 0x0000 /* 10Mbps half-duplex */
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#define MDIO_USXGMII_10FULL 0x1000 /* 10Mbps full-duplex */
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#define MDIO_USXGMII_100 0x0200 /* 100Mbps */
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#define MDIO_USXGMII_100HALF 0x0200 /* 100Mbps half-duplex */
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#define MDIO_USXGMII_100FULL 0x1200 /* 100Mbps full-duplex */
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#define MDIO_USXGMII_1000 0x0400 /* 1000Mbps */
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#define MDIO_USXGMII_1000HALF 0x0400 /* 1000Mbps half-duplex */
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#define MDIO_USXGMII_1000FULL 0x1400 /* 1000Mbps full-duplex */
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#define MDIO_USXGMII_10G 0x0600 /* 10Gbps */
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#define MDIO_USXGMII_10GHALF 0x0600 /* 10Gbps half-duplex */
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#define MDIO_USXGMII_10GFULL 0x1600 /* 10Gbps full-duplex */
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#define MDIO_USXGMII_2500 0x0800 /* 2500Mbps */
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#define MDIO_USXGMII_2500HALF 0x0800 /* 2500Mbps half-duplex */
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#define MDIO_USXGMII_2500FULL 0x1800 /* 2500Mbps full-duplex */
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#define MDIO_USXGMII_5000 0x0a00 /* 5000Mbps */
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#define MDIO_USXGMII_5000HALF 0x0a00 /* 5000Mbps half-duplex */
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#define MDIO_USXGMII_5000FULL 0x1a00 /* 5000Mbps full-duplex */
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#define MDIO_USXGMII_LINK 0x8000 /* PHY link with copper-side partner */
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#endif /* _UAPI__LINUX_MDIO_H__ */
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