/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* 10G controller driver for Samsung Exynos SoCs
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Siva Reddy Kallam <siva.kallam@samsung.com>
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*/
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#ifndef __SXGBE_PLATFORM_H__
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#define __SXGBE_PLATFORM_H__
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#include <linux/phy.h>
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/* MDC Clock Selection define*/
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#define SXGBE_CSR_100_150M 0x0 /* MDC = clk_scr_i/62 */
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#define SXGBE_CSR_150_250M 0x1 /* MDC = clk_scr_i/102 */
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#define SXGBE_CSR_250_300M 0x2 /* MDC = clk_scr_i/122 */
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#define SXGBE_CSR_300_350M 0x3 /* MDC = clk_scr_i/142 */
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#define SXGBE_CSR_350_400M 0x4 /* MDC = clk_scr_i/162 */
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#define SXGBE_CSR_400_500M 0x5 /* MDC = clk_scr_i/202 */
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/* Platfrom data for platform device structure's
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* platform_data field
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*/
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struct sxgbe_mdio_bus_data {
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unsigned int phy_mask;
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int *irqs;
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int probed_phy_irq;
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};
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struct sxgbe_dma_cfg {
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int pbl;
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int fixed_burst;
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int burst_map;
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int adv_addr_mode;
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};
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struct sxgbe_plat_data {
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char *phy_bus_name;
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int bus_id;
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int phy_addr;
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phy_interface_t interface;
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struct sxgbe_mdio_bus_data *mdio_bus_data;
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struct sxgbe_dma_cfg *dma_cfg;
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int clk_csr;
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int pmt;
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int force_sf_dma_mode;
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int force_thresh_dma_mode;
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int riwt_off;
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};
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#endif /* __SXGBE_PLATFORM_H__ */
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