/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* UEFI Common Platform Error Record
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*
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* Copyright (C) 2010, Intel Corp.
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* Author: Huang Ying <ying.huang@intel.com>
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*/
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#ifndef LINUX_CPER_H
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#define LINUX_CPER_H
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#include <linux/uuid.h>
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#include <linux/trace_seq.h>
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/* CPER record signature and the size */
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#define CPER_SIG_RECORD "CPER"
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#define CPER_SIG_SIZE 4
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/* Used in signature_end field in struct cper_record_header */
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#define CPER_SIG_END 0xffffffff
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/*
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* CPER record header revision, used in revision field in struct
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* cper_record_header
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*/
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#define CPER_RECORD_REV 0x0100
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/*
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* CPER record length contains the CPER fields which are relevant for further
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* handling of a memory error in userspace (we don't carry all the fields
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* defined in the UEFI spec because some of them don't make any sense.)
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* Currently, a length of 256 should be more than enough.
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*/
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#define CPER_REC_LEN 256
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/*
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* Severity definition for error_severity in struct cper_record_header
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* and section_severity in struct cper_section_descriptor
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*/
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enum {
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CPER_SEV_RECOVERABLE,
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CPER_SEV_FATAL,
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CPER_SEV_CORRECTED,
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CPER_SEV_INFORMATIONAL,
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};
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/*
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* Validation bits definition for validation_bits in struct
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* cper_record_header. If set, corresponding fields in struct
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* cper_record_header contain valid information.
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*/
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#define CPER_VALID_PLATFORM_ID 0x0001
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#define CPER_VALID_TIMESTAMP 0x0002
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#define CPER_VALID_PARTITION_ID 0x0004
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/*
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* Notification type used to generate error record, used in
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* notification_type in struct cper_record_header. These UUIDs are defined
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* in the UEFI spec v2.7, sec N.2.1.
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*/
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/* Corrected Machine Check */
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#define CPER_NOTIFY_CMC \
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GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
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0xEB, 0xD4, 0xF8, 0x90)
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/* Corrected Platform Error */
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#define CPER_NOTIFY_CPE \
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GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \
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0xF2, 0x7E, 0xBE, 0xEE)
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/* Machine Check Exception */
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#define CPER_NOTIFY_MCE \
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GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \
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0xE1, 0x49, 0x13, 0xBB)
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/* PCI Express Error */
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#define CPER_NOTIFY_PCIE \
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GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \
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0xAF, 0x67, 0xC1, 0x04)
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/* INIT Record (for IPF) */
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#define CPER_NOTIFY_INIT \
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GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \
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0xD3, 0x9B, 0xC9, 0x8E)
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/* Non-Maskable Interrupt */
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#define CPER_NOTIFY_NMI \
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GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \
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0x85, 0xD6, 0xE9, 0x8A)
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/* BOOT Error Record */
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#define CPER_NOTIFY_BOOT \
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GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \
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0xD4, 0x64, 0xB3, 0x8F)
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/* DMA Remapping Error */
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#define CPER_NOTIFY_DMAR \
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GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \
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0x72, 0x2D, 0xEB, 0x41)
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/*
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* Flags bits definitions for flags in struct cper_record_header
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* If set, the error has been recovered
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*/
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#define CPER_HW_ERROR_FLAGS_RECOVERED 0x1
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/* If set, the error is for previous boot */
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#define CPER_HW_ERROR_FLAGS_PREVERR 0x2
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/* If set, the error is injected for testing */
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#define CPER_HW_ERROR_FLAGS_SIMULATED 0x4
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/*
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* CPER section header revision, used in revision field in struct
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* cper_section_descriptor
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*/
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#define CPER_SEC_REV 0x0100
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/*
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* Validation bits definition for validation_bits in struct
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* cper_section_descriptor. If set, corresponding fields in struct
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* cper_section_descriptor contain valid information.
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*/
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#define CPER_SEC_VALID_FRU_ID 0x1
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#define CPER_SEC_VALID_FRU_TEXT 0x2
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/*
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* Flags bits definitions for flags in struct cper_section_descriptor
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*
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* If set, the section is associated with the error condition
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* directly, and should be focused on
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*/
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#define CPER_SEC_PRIMARY 0x0001
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/*
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* If set, the error was not contained within the processor or memory
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* hierarchy and the error may have propagated to persistent storage
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* or network
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*/
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#define CPER_SEC_CONTAINMENT_WARNING 0x0002
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/* If set, the component must be re-initialized or re-enabled prior to use */
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#define CPER_SEC_RESET 0x0004
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/* If set, Linux may choose to discontinue use of the resource */
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#define CPER_SEC_ERROR_THRESHOLD_EXCEEDED 0x0008
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/*
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* If set, resource could not be queried for error information due to
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* conflicts with other system software or resources. Some fields of
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* the section will be invalid
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*/
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#define CPER_SEC_RESOURCE_NOT_ACCESSIBLE 0x0010
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/*
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* If set, action has been taken to ensure error containment (such as
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* poisoning data), but the error has not been fully corrected and the
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* data has not been consumed. Linux may choose to take further
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* corrective action before the data is consumed
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*/
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#define CPER_SEC_LATENT_ERROR 0x0020
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/*
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* Section type definitions, used in section_type field in struct
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* cper_section_descriptor. These UUIDs are defined in the UEFI spec
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* v2.7, sec N.2.2.
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*/
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/* Processor Generic */
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#define CPER_SEC_PROC_GENERIC \
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GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \
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0x93, 0xC4, 0xF3, 0xDB)
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/* Processor Specific: X86/X86_64 */
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#define CPER_SEC_PROC_IA \
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GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \
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0x24, 0x2B, 0x6E, 0x1D)
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/* Processor Specific: IA64 */
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#define CPER_SEC_PROC_IPF \
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GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00, \
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0x80, 0xC7, 0x3C, 0x88, 0x81)
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/* Processor Specific: ARM */
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#define CPER_SEC_PROC_ARM \
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GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05, \
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0x1D, 0x5D, 0x46, 0xB0)
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/* Platform Memory */
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#define CPER_SEC_PLATFORM_MEM \
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GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \
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0xED, 0x7C, 0x83, 0xB1)
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#define CPER_SEC_PCIE \
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GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D, \
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0xCB, 0x3C, 0x6F, 0x35)
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/* Firmware Error Record Reference */
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#define CPER_SEC_FW_ERR_REC_REF \
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GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72, \
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0x9C, 0x8E, 0x69, 0xED)
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/* PCI/PCI-X Bus */
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#define CPER_SEC_PCI_X_BUS \
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GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA, \
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0xD3, 0xF9, 0xC9, 0xDD)
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/* PCI Component/Device */
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#define CPER_SEC_PCI_DEV \
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GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06, \
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0x8B, 0x00, 0x13, 0x26)
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#define CPER_SEC_DMAR_GENERIC \
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GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62, \
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0xDE, 0x3E, 0x2C, 0x64)
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/* Intel VT for Directed I/O specific DMAr */
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#define CPER_SEC_DMAR_VT \
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GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE, \
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0xDD, 0x93, 0xE8, 0xCF)
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/* IOMMU specific DMAr */
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#define CPER_SEC_DMAR_IOMMU \
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GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F, \
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0xDF, 0xAA, 0x84, 0xEC)
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#define CPER_PROC_VALID_TYPE 0x0001
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#define CPER_PROC_VALID_ISA 0x0002
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#define CPER_PROC_VALID_ERROR_TYPE 0x0004
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#define CPER_PROC_VALID_OPERATION 0x0008
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#define CPER_PROC_VALID_FLAGS 0x0010
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#define CPER_PROC_VALID_LEVEL 0x0020
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#define CPER_PROC_VALID_VERSION 0x0040
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#define CPER_PROC_VALID_BRAND_INFO 0x0080
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#define CPER_PROC_VALID_ID 0x0100
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#define CPER_PROC_VALID_TARGET_ADDRESS 0x0200
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#define CPER_PROC_VALID_REQUESTOR_ID 0x0400
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#define CPER_PROC_VALID_RESPONDER_ID 0x0800
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#define CPER_PROC_VALID_IP 0x1000
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#define CPER_MEM_VALID_ERROR_STATUS 0x0001
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#define CPER_MEM_VALID_PA 0x0002
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#define CPER_MEM_VALID_PA_MASK 0x0004
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#define CPER_MEM_VALID_NODE 0x0008
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#define CPER_MEM_VALID_CARD 0x0010
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#define CPER_MEM_VALID_MODULE 0x0020
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#define CPER_MEM_VALID_BANK 0x0040
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#define CPER_MEM_VALID_DEVICE 0x0080
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#define CPER_MEM_VALID_ROW 0x0100
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#define CPER_MEM_VALID_COLUMN 0x0200
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#define CPER_MEM_VALID_BIT_POSITION 0x0400
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#define CPER_MEM_VALID_REQUESTOR_ID 0x0800
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#define CPER_MEM_VALID_RESPONDER_ID 0x1000
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#define CPER_MEM_VALID_TARGET_ID 0x2000
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#define CPER_MEM_VALID_ERROR_TYPE 0x4000
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#define CPER_MEM_VALID_RANK_NUMBER 0x8000
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#define CPER_MEM_VALID_CARD_HANDLE 0x10000
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#define CPER_MEM_VALID_MODULE_HANDLE 0x20000
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#define CPER_MEM_VALID_ROW_EXT 0x40000
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#define CPER_MEM_VALID_BANK_GROUP 0x80000
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#define CPER_MEM_VALID_BANK_ADDRESS 0x100000
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#define CPER_MEM_VALID_CHIP_ID 0x200000
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#define CPER_MEM_EXT_ROW_MASK 0x3
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#define CPER_MEM_EXT_ROW_SHIFT 16
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#define CPER_MEM_BANK_ADDRESS_MASK 0xff
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#define CPER_MEM_BANK_GROUP_SHIFT 8
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#define CPER_MEM_CHIP_ID_SHIFT 5
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#define CPER_PCIE_VALID_PORT_TYPE 0x0001
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#define CPER_PCIE_VALID_VERSION 0x0002
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#define CPER_PCIE_VALID_COMMAND_STATUS 0x0004
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#define CPER_PCIE_VALID_DEVICE_ID 0x0008
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#define CPER_PCIE_VALID_SERIAL_NUMBER 0x0010
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#define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS 0x0020
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#define CPER_PCIE_VALID_CAPABILITY 0x0040
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#define CPER_PCIE_VALID_AER_INFO 0x0080
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#define CPER_PCIE_SLOT_SHIFT 3
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#define CPER_ARM_VALID_MPIDR BIT(0)
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#define CPER_ARM_VALID_AFFINITY_LEVEL BIT(1)
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#define CPER_ARM_VALID_RUNNING_STATE BIT(2)
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#define CPER_ARM_VALID_VENDOR_INFO BIT(3)
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#define CPER_ARM_INFO_VALID_MULTI_ERR BIT(0)
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#define CPER_ARM_INFO_VALID_FLAGS BIT(1)
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#define CPER_ARM_INFO_VALID_ERR_INFO BIT(2)
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#define CPER_ARM_INFO_VALID_VIRT_ADDR BIT(3)
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#define CPER_ARM_INFO_VALID_PHYSICAL_ADDR BIT(4)
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#define CPER_ARM_INFO_FLAGS_FIRST BIT(0)
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#define CPER_ARM_INFO_FLAGS_LAST BIT(1)
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#define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2)
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#define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3)
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#define CPER_ARM_CACHE_ERROR 0
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#define CPER_ARM_TLB_ERROR 1
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#define CPER_ARM_BUS_ERROR 2
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#define CPER_ARM_VENDOR_ERROR 3
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#define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR
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#define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0)
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#define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1)
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#define CPER_ARM_ERR_VALID_LEVEL BIT(2)
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#define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3)
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#define CPER_ARM_ERR_VALID_CORRECTED BIT(4)
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#define CPER_ARM_ERR_VALID_PRECISE_PC BIT(5)
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#define CPER_ARM_ERR_VALID_RESTARTABLE_PC BIT(6)
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#define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE BIT(7)
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#define CPER_ARM_ERR_VALID_TIME_OUT BIT(8)
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#define CPER_ARM_ERR_VALID_ADDRESS_SPACE BIT(9)
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#define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES BIT(10)
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#define CPER_ARM_ERR_VALID_ACCESS_MODE BIT(11)
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#define CPER_ARM_ERR_TRANSACTION_SHIFT 16
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#define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0)
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#define CPER_ARM_ERR_OPERATION_SHIFT 18
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#define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0)
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#define CPER_ARM_ERR_LEVEL_SHIFT 22
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#define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0)
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#define CPER_ARM_ERR_PC_CORRUPT_SHIFT 25
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#define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0)
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#define CPER_ARM_ERR_CORRECTED_SHIFT 26
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#define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0)
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#define CPER_ARM_ERR_PRECISE_PC_SHIFT 27
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#define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0)
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#define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT 28
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#define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0)
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#define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT 29
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#define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0)
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#define CPER_ARM_ERR_TIME_OUT_SHIFT 31
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#define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0)
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#define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT 32
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#define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0)
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#define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT 34
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#define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK GENMASK(8,0)
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#define CPER_ARM_ERR_ACCESS_MODE_SHIFT 43
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#define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0)
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/*
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* All tables and structs must be byte-packed to match CPER
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* specification, since the tables are provided by the system BIOS
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*/
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#pragma pack(1)
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/* Record Header, UEFI v2.7 sec N.2.1 */
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struct cper_record_header {
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char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */
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u16 revision; /* must be CPER_RECORD_REV */
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u32 signature_end; /* must be CPER_SIG_END */
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u16 section_count;
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u32 error_severity;
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u32 validation_bits;
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u32 record_length;
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u64 timestamp;
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guid_t platform_id;
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guid_t partition_id;
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guid_t creator_id;
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guid_t notification_type;
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u64 record_id;
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u32 flags;
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u64 persistence_information;
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u8 reserved[12]; /* must be zero */
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};
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/* Section Descriptor, UEFI v2.7 sec N.2.2 */
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struct cper_section_descriptor {
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u32 section_offset; /* Offset in bytes of the
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* section body from the base
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* of the record header */
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u32 section_length;
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u16 revision; /* must be CPER_RECORD_REV */
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u8 validation_bits;
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u8 reserved; /* must be zero */
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u32 flags;
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guid_t section_type;
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guid_t fru_id;
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u32 section_severity;
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u8 fru_text[20];
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};
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/* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
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struct cper_sec_proc_generic {
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u64 validation_bits;
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u8 proc_type;
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u8 proc_isa;
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u8 proc_error_type;
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u8 operation;
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u8 flags;
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u8 level;
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u16 reserved;
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u64 cpu_version;
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char cpu_brand[128];
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u64 proc_id;
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u64 target_addr;
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u64 requestor_id;
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u64 responder_id;
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u64 ip;
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};
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/* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
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struct cper_sec_proc_ia {
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u64 validation_bits;
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u64 lapic_id;
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u8 cpuid[48];
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};
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/* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
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struct cper_ia_err_info {
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guid_t err_type;
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u64 validation_bits;
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u64 check_info;
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u64 target_id;
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u64 requestor_id;
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u64 responder_id;
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u64 ip;
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};
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/* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
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struct cper_ia_proc_ctx {
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u16 reg_ctx_type;
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u16 reg_arr_size;
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u32 msr_addr;
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u64 mm_reg_addr;
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};
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/* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
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struct cper_sec_proc_arm {
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u32 validation_bits;
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u16 err_info_num; /* Number of Processor Error Info */
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u16 context_info_num; /* Number of Processor Context Info Records*/
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u32 section_length;
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u8 affinity_level;
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u8 reserved[3]; /* must be zero */
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u64 mpidr;
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u64 midr;
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u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */
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u32 psci_state;
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};
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/* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
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struct cper_arm_err_info {
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u8 version;
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u8 length;
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u16 validation_bits;
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u8 type;
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u16 multiple_error;
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u8 flags;
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u64 error_info;
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u64 virt_fault_addr;
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u64 physical_fault_addr;
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};
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/* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
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struct cper_arm_ctx_info {
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u16 version;
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u16 type;
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u32 size;
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};
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/* Old Memory Error Section, UEFI v2.1, v2.2 */
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struct cper_sec_mem_err_old {
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u64 validation_bits;
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u64 error_status;
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u64 physical_addr;
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u64 physical_addr_mask;
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u16 node;
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u16 card;
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u16 module;
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u16 bank;
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u16 device;
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u16 row;
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u16 column;
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u16 bit_pos;
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u64 requestor_id;
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u64 responder_id;
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u64 target_id;
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u8 error_type;
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};
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/* Memory Error Section (UEFI >= v2.3), UEFI v2.8 sec N.2.5 */
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struct cper_sec_mem_err {
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u64 validation_bits;
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u64 error_status;
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u64 physical_addr;
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u64 physical_addr_mask;
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u16 node;
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u16 card;
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u16 module;
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u16 bank;
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u16 device;
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u16 row;
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u16 column;
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u16 bit_pos;
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u64 requestor_id;
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u64 responder_id;
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u64 target_id;
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u8 error_type;
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u8 extended;
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u16 rank;
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u16 mem_array_handle; /* "card handle" in UEFI 2.4 */
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u16 mem_dev_handle; /* "module handle" in UEFI 2.4 */
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};
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struct cper_mem_err_compact {
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u64 validation_bits;
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u16 node;
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u16 card;
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u16 module;
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u16 bank;
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u16 device;
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u16 row;
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u16 column;
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u16 bit_pos;
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u64 requestor_id;
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u64 responder_id;
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u64 target_id;
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u16 rank;
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u16 mem_array_handle;
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u16 mem_dev_handle;
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u8 extended;
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};
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static inline u32 cper_get_mem_extension(u64 mem_valid, u8 mem_extended)
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{
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if (!(mem_valid & CPER_MEM_VALID_ROW_EXT))
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return 0;
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return (mem_extended & CPER_MEM_EXT_ROW_MASK) << CPER_MEM_EXT_ROW_SHIFT;
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}
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/* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
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struct cper_sec_pcie {
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u64 validation_bits;
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u32 port_type;
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struct {
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u8 minor;
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u8 major;
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u8 reserved[2];
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} version;
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u16 command;
|
u16 status;
|
u32 reserved;
|
struct {
|
u16 vendor_id;
|
u16 device_id;
|
u8 class_code[3];
|
u8 function;
|
u8 device;
|
u16 segment;
|
u8 bus;
|
u8 secondary_bus;
|
u16 slot;
|
u8 reserved;
|
} device_id;
|
struct {
|
u32 lower;
|
u32 upper;
|
} serial_number;
|
struct {
|
u16 secondary_status;
|
u16 control;
|
} bridge;
|
u8 capability[60];
|
u8 aer_info[96];
|
};
|
|
/* Firmware Error Record Reference, UEFI v2.7 sec N.2.10 */
|
struct cper_sec_fw_err_rec_ref {
|
u8 record_type;
|
u8 revision;
|
u8 reserved[6];
|
u64 record_identifier;
|
guid_t record_identifier_guid;
|
};
|
|
/* Reset to default packing */
|
#pragma pack()
|
|
extern const char *const cper_proc_error_type_strs[4];
|
|
u64 cper_next_record_id(void);
|
const char *cper_severity_str(unsigned int);
|
const char *cper_mem_err_type_str(unsigned int);
|
void cper_print_bits(const char *prefix, unsigned int bits,
|
const char * const strs[], unsigned int strs_size);
|
void cper_mem_err_pack(const struct cper_sec_mem_err *,
|
struct cper_mem_err_compact *);
|
const char *cper_mem_err_unpack(struct trace_seq *,
|
struct cper_mem_err_compact *);
|
void cper_print_proc_arm(const char *pfx,
|
const struct cper_sec_proc_arm *proc);
|
void cper_print_proc_ia(const char *pfx,
|
const struct cper_sec_proc_ia *proc);
|
|
#endif
|
