/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_IRQFLAGS_H
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#define __ASM_IRQFLAGS_H
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#include <asm/alternative.h>
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#include <asm/barrier.h>
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#include <asm/ptrace.h>
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#include <asm/sysreg.h>
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#define IRQMASK_I_BIT PSR_I_BIT
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#define IRQMASK_I_POS 7
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#define IRQMASK_i_POS 31
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/*
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* Aarch64 has flags for masking: Debug, Asynchronous (serror), Interrupts and
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* FIQ exceptions, in the 'daif' register. We mask and unmask them in 'dai'
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* order:
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* Masking debug exceptions causes all other exceptions to be masked too/
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* Masking SError masks irq, but not debug exceptions. Masking irqs has no
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* side effects for other flags. Keeping to this order makes it easier for
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* entry.S to know which exceptions should be unmasked.
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*
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* FIQ is never expected, but we mask it when we disable debug exceptions, and
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* unmask it at all other times.
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*/
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/*
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* CPU interrupt mask handling.
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*/
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static inline void native_irq_enable(void)
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{
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if (system_has_prio_mask_debugging()) {
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u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1);
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WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);
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}
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asm volatile(ALTERNATIVE(
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"msr daifclr, #2 // native_irq_enable",
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__msr_s(SYS_ICC_PMR_EL1, "%0"),
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ARM64_HAS_IRQ_PRIO_MASKING)
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:
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: "r" ((unsigned long) GIC_PRIO_IRQON)
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: "memory");
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pmr_sync();
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}
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static inline void native_irq_disable(void)
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{
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if (system_has_prio_mask_debugging()) {
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u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1);
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WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);
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}
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asm volatile(ALTERNATIVE(
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"msr daifset, #2 // native_irq_disable",
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__msr_s(SYS_ICC_PMR_EL1, "%0"),
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ARM64_HAS_IRQ_PRIO_MASKING)
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:
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: "r" ((unsigned long) GIC_PRIO_IRQOFF)
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: "memory");
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}
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static inline void native_irq_sync(void)
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{
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native_irq_enable();
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isb();
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native_irq_disable();
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}
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/*
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* Save the current interrupt enable state.
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*/
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static inline unsigned long native_save_flags(void)
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{
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unsigned long flags;
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asm volatile(ALTERNATIVE(
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"mrs %0, daif",
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__mrs_s("%0", SYS_ICC_PMR_EL1),
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ARM64_HAS_IRQ_PRIO_MASKING)
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: "=&r" (flags)
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:
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: "memory");
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return flags;
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}
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static inline int native_irqs_disabled_flags(unsigned long flags)
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{
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int res;
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asm volatile(ALTERNATIVE(
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"and %w0, %w1, #" __stringify(PSR_I_BIT),
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"eor %w0, %w1, #" __stringify(GIC_PRIO_IRQON),
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ARM64_HAS_IRQ_PRIO_MASKING)
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: "=&r" (res)
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: "r" ((int) flags)
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: "memory");
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return res;
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}
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static inline unsigned long native_irq_save(void)
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{
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unsigned long flags;
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flags = native_save_flags();
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/*
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* There are too many states with IRQs disabled, just keep the current
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* state if interrupts are already disabled/masked.
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*/
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if (!native_irqs_disabled_flags(flags))
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native_irq_disable();
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return flags;
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}
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/*
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* restore saved IRQ state
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*/
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static inline void native_irq_restore(unsigned long flags)
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{
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asm volatile(ALTERNATIVE(
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"msr daif, %0",
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__msr_s(SYS_ICC_PMR_EL1, "%0"),
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ARM64_HAS_IRQ_PRIO_MASKING)
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:
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: "r" (flags)
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: "memory");
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pmr_sync();
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}
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static inline bool native_irqs_disabled(void)
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{
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unsigned long flags = native_save_flags();
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return native_irqs_disabled_flags(flags);
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}
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#include <asm/irq_pipeline.h>
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#endif /* __ASM_IRQFLAGS_H */
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