/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/include/asm/pgtable-3level-hwdef.h
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*
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* Copyright (C) 2011 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*/
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#ifndef _ASM_PGTABLE_3LEVEL_HWDEF_H
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#define _ASM_PGTABLE_3LEVEL_HWDEF_H
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/*
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* Hardware page table definitions.
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*
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* + Level 1/2 descriptor
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* - common
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*/
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#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
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#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
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#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
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#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
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#define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
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#define PMD_BIT4 (_AT(pmdval_t, 0))
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#define PMD_DOMAIN(x) (_AT(pmdval_t, 0))
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#define PMD_APTABLE_SHIFT (61)
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#define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT)
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#define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59)
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/*
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* - section
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*/
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#define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2)
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#define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3)
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#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */
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#define PMD_SECT_AP2 (_AT(pmdval_t, 1) << 7) /* read only */
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#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
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#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
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#define PMD_SECT_nG (_AT(pmdval_t, 1) << 11)
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#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
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#define PMD_SECT_XN (_AT(pmdval_t, 1) << 54)
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#define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0))
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#define PMD_SECT_AP_READ (_AT(pmdval_t, 0))
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#define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6)
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#define PMD_SECT_TEX(x) (_AT(pmdval_t, 0))
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define PMD_SECT_UNCACHED (_AT(pmdval_t, 0) << 2) /* strongly ordered */
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#define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */
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#define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) /* normal inner write-through */
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#define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) /* normal inner write-back */
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#define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */
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#define PMD_SECT_CACHE_MASK (_AT(pmdval_t, 7) << 2)
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/*
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* + Level 3 descriptor (PTE)
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*/
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#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
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#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
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#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
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#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
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#define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */
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#define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */
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#define PTE_AP2 (_AT(pteval_t, 1) << 7) /* AP[2] */
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#define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
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#define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
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#define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */
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#define PTE_EXT_PXN (_AT(pteval_t, 1) << 53) /* PXN */
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#define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */
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/*
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* 40-bit physical address supported.
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*/
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#define PHYS_MASK_SHIFT (40)
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#define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1)
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/*
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* TTBR0/TTBR1 split (PAGE_OFFSET):
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* 0x40000000: T0SZ = 2, T1SZ = 0 (not used)
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* 0x80000000: T0SZ = 0, T1SZ = 1
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* 0xc0000000: T0SZ = 0, T1SZ = 2
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*
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* Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
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* booting secondary CPUs would end up using TTBR1 for the identity
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* mapping set up in TTBR0.
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*/
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#if defined CONFIG_VMSPLIT_2G
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#define TTBR1_OFFSET 16 /* skip two L1 entries */
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#elif defined CONFIG_VMSPLIT_3G
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#define TTBR1_OFFSET (4096 * (1 + 3)) /* only L2, skip pgd + 3*pmd */
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#else
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#define TTBR1_OFFSET 0
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#endif
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#define TTBR1_SIZE (((PAGE_OFFSET >> 30) - 1) << 16)
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#endif
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