/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _LMC_IOCTL_H_
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#define _LMC_IOCTL_H_
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/* $Id: lmc_ioctl.h,v 1.15 2000/04/06 12:16:43 asj Exp $ */
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/*
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* Copyright (c) 1997-2000 LAN Media Corporation (LMC)
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* All rights reserved. www.lanmedia.com
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*
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* This code is written by:
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* Andrew Stanley-Jones (asj@cban.com)
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* Rob Braun (bbraun@vix.com),
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* Michael Graff (explorer@vix.com) and
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* Matt Thomas (matt@3am-software.com).
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*/
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#define LMCIOCGINFO SIOCDEVPRIVATE+3 /* get current state */
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#define LMCIOCSINFO SIOCDEVPRIVATE+4 /* set state to user values */
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#define LMCIOCGETLMCSTATS SIOCDEVPRIVATE+5
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#define LMCIOCCLEARLMCSTATS SIOCDEVPRIVATE+6
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#define LMCIOCDUMPEVENTLOG SIOCDEVPRIVATE+7
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#define LMCIOCGETXINFO SIOCDEVPRIVATE+8
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#define LMCIOCSETCIRCUIT SIOCDEVPRIVATE+9
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#define LMCIOCUNUSEDATM SIOCDEVPRIVATE+10
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#define LMCIOCRESET SIOCDEVPRIVATE+11
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#define LMCIOCT1CONTROL SIOCDEVPRIVATE+12
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#define LMCIOCIFTYPE SIOCDEVPRIVATE+13
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#define LMCIOCXILINX SIOCDEVPRIVATE+14
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#define LMC_CARDTYPE_UNKNOWN -1
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#define LMC_CARDTYPE_HSSI 1 /* probed card is a HSSI card */
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#define LMC_CARDTYPE_DS3 2 /* probed card is a DS3 card */
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#define LMC_CARDTYPE_SSI 3 /* probed card is a SSI card */
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#define LMC_CARDTYPE_T1 4 /* probed card is a T1 card */
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#define LMC_CTL_CARDTYPE_LMC5200 0 /* HSSI */
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#define LMC_CTL_CARDTYPE_LMC5245 1 /* DS3 */
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#define LMC_CTL_CARDTYPE_LMC1000 2 /* SSI, V.35 */
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#define LMC_CTL_CARDTYPE_LMC1200 3 /* DS1 */
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#define LMC_CTL_OFF 0 /* generic OFF value */
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#define LMC_CTL_ON 1 /* generic ON value */
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#define LMC_CTL_CLOCK_SOURCE_EXT 0 /* clock off line */
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#define LMC_CTL_CLOCK_SOURCE_INT 1 /* internal clock */
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#define LMC_CTL_CRC_LENGTH_16 16
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#define LMC_CTL_CRC_LENGTH_32 32
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#define LMC_CTL_CRC_BYTESIZE_2 2
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#define LMC_CTL_CRC_BYTESIZE_4 4
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#define LMC_CTL_CABLE_LENGTH_LT_100FT 0 /* DS3 cable < 100 feet */
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#define LMC_CTL_CABLE_LENGTH_GT_100FT 1 /* DS3 cable >= 100 feet */
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#define LMC_CTL_CIRCUIT_TYPE_E1 0
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#define LMC_CTL_CIRCUIT_TYPE_T1 1
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/*
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* IFTYPE defines
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*/
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#define LMC_PPP 1 /* use generic HDLC interface */
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#define LMC_NET 2 /* use direct net interface */
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#define LMC_RAW 3 /* use direct net interface */
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/*
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* These are not in the least IOCTL related, but I want them common.
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*/
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/*
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* assignments for the GPIO register on the DEC chip (common)
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*/
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#define LMC_GEP_INIT 0x01 /* 0: */
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#define LMC_GEP_RESET 0x02 /* 1: */
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#define LMC_GEP_MODE 0x10 /* 4: */
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#define LMC_GEP_DP 0x20 /* 5: */
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#define LMC_GEP_DATA 0x40 /* 6: serial out */
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#define LMC_GEP_CLK 0x80 /* 7: serial clock */
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/*
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* HSSI GPIO assignments
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*/
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#define LMC_GEP_HSSI_ST 0x04 /* 2: receive timing sense (deprecated) */
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#define LMC_GEP_HSSI_CLOCK 0x08 /* 3: clock source */
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/*
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* T1 GPIO assignments
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*/
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#define LMC_GEP_SSI_GENERATOR 0x04 /* 2: enable prog freq gen serial i/f */
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#define LMC_GEP_SSI_TXCLOCK 0x08 /* 3: provide clock on TXCLOCK output */
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/*
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* Common MII16 bits
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*/
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#define LMC_MII16_LED0 0x0080
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#define LMC_MII16_LED1 0x0100
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#define LMC_MII16_LED2 0x0200
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#define LMC_MII16_LED3 0x0400 /* Error, and the red one */
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#define LMC_MII16_LED_ALL 0x0780 /* LED bit mask */
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#define LMC_MII16_FIFO_RESET 0x0800
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/*
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* definitions for HSSI
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*/
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#define LMC_MII16_HSSI_TA 0x0001
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#define LMC_MII16_HSSI_CA 0x0002
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#define LMC_MII16_HSSI_LA 0x0004
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#define LMC_MII16_HSSI_LB 0x0008
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#define LMC_MII16_HSSI_LC 0x0010
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#define LMC_MII16_HSSI_TM 0x0020
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#define LMC_MII16_HSSI_CRC 0x0040
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/*
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* assignments for the MII register 16 (DS3)
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*/
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#define LMC_MII16_DS3_ZERO 0x0001
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#define LMC_MII16_DS3_TRLBK 0x0002
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#define LMC_MII16_DS3_LNLBK 0x0004
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#define LMC_MII16_DS3_RAIS 0x0008
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#define LMC_MII16_DS3_TAIS 0x0010
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#define LMC_MII16_DS3_BIST 0x0020
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#define LMC_MII16_DS3_DLOS 0x0040
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#define LMC_MII16_DS3_CRC 0x1000
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#define LMC_MII16_DS3_SCRAM 0x2000
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#define LMC_MII16_DS3_SCRAM_LARS 0x4000
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/* Note: 2 pairs of LEDs where swapped by mistake
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* in Xilinx code for DS3 & DS1 adapters */
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#define LMC_DS3_LED0 0x0100 /* bit 08 yellow */
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#define LMC_DS3_LED1 0x0080 /* bit 07 blue */
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#define LMC_DS3_LED2 0x0400 /* bit 10 green */
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#define LMC_DS3_LED3 0x0200 /* bit 09 red */
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/*
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* framer register 0 and 7 (7 is latched and reset on read)
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*/
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#define LMC_FRAMER_REG0_DLOS 0x80 /* digital loss of service */
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#define LMC_FRAMER_REG0_OOFS 0x40 /* out of frame sync */
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#define LMC_FRAMER_REG0_AIS 0x20 /* alarm indication signal */
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#define LMC_FRAMER_REG0_CIS 0x10 /* channel idle */
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#define LMC_FRAMER_REG0_LOC 0x08 /* loss of clock */
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/*
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* Framer register 9 contains the blue alarm signal
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*/
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#define LMC_FRAMER_REG9_RBLUE 0x02 /* Blue alarm failure */
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/*
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* Framer register 0x10 contains xbit error
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*/
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#define LMC_FRAMER_REG10_XBIT 0x01 /* X bit error alarm failure */
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/*
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* And SSI, LMC1000
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*/
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#define LMC_MII16_SSI_DTR 0x0001 /* DTR output RW */
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#define LMC_MII16_SSI_DSR 0x0002 /* DSR input RO */
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#define LMC_MII16_SSI_RTS 0x0004 /* RTS output RW */
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#define LMC_MII16_SSI_CTS 0x0008 /* CTS input RO */
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#define LMC_MII16_SSI_DCD 0x0010 /* DCD input RO */
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#define LMC_MII16_SSI_RI 0x0020 /* RI input RO */
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#define LMC_MII16_SSI_CRC 0x1000 /* CRC select - RW */
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/*
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* bits 0x0080 through 0x0800 are generic, and described
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* above with LMC_MII16_LED[0123] _LED_ALL, and _FIFO_RESET
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*/
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#define LMC_MII16_SSI_LL 0x1000 /* LL output RW */
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#define LMC_MII16_SSI_RL 0x2000 /* RL output RW */
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#define LMC_MII16_SSI_TM 0x4000 /* TM input RO */
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#define LMC_MII16_SSI_LOOP 0x8000 /* loopback enable RW */
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/*
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* Some of the MII16 bits are mirrored in the MII17 register as well,
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* but let's keep thing separate for now, and get only the cable from
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* the MII17.
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*/
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#define LMC_MII17_SSI_CABLE_MASK 0x0038 /* mask to extract the cable type */
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#define LMC_MII17_SSI_CABLE_SHIFT 3 /* shift to extract the cable type */
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/*
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* And T1, LMC1200
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*/
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#define LMC_MII16_T1_UNUSED1 0x0003
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#define LMC_MII16_T1_XOE 0x0004
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#define LMC_MII16_T1_RST 0x0008 /* T1 chip reset - RW */
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#define LMC_MII16_T1_Z 0x0010 /* output impedance T1=1, E1=0 output - RW */
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#define LMC_MII16_T1_INTR 0x0020 /* interrupt from 8370 - RO */
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#define LMC_MII16_T1_ONESEC 0x0040 /* one second square wave - ro */
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#define LMC_MII16_T1_LED0 0x0100
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#define LMC_MII16_T1_LED1 0x0080
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#define LMC_MII16_T1_LED2 0x0400
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#define LMC_MII16_T1_LED3 0x0200
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#define LMC_MII16_T1_FIFO_RESET 0x0800
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#define LMC_MII16_T1_CRC 0x1000 /* CRC select - RW */
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#define LMC_MII16_T1_UNUSED2 0xe000
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/* 8370 framer registers */
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#define T1FRAMER_ALARM1_STATUS 0x47
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#define T1FRAMER_ALARM2_STATUS 0x48
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#define T1FRAMER_FERR_LSB 0x50
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#define T1FRAMER_FERR_MSB 0x51 /* framing bit error counter */
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#define T1FRAMER_LCV_LSB 0x54
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#define T1FRAMER_LCV_MSB 0x55 /* line code violation counter */
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#define T1FRAMER_AERR 0x5A
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/* mask for the above AERR register */
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#define T1FRAMER_LOF_MASK (0x0f0) /* receive loss of frame */
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#define T1FRAMER_COFA_MASK (0x0c0) /* change of frame alignment */
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#define T1FRAMER_SEF_MASK (0x03) /* severely errored frame */
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/* 8370 framer register ALM1 (0x47) values
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* used to determine link status
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*/
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#define T1F_SIGFRZ 0x01 /* signaling freeze */
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#define T1F_RLOF 0x02 /* receive loss of frame alignment */
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#define T1F_RLOS 0x04 /* receive loss of signal */
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#define T1F_RALOS 0x08 /* receive analog loss of signal or RCKI loss of clock */
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#define T1F_RAIS 0x10 /* receive alarm indication signal */
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#define T1F_UNUSED 0x20
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#define T1F_RYEL 0x40 /* receive yellow alarm */
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#define T1F_RMYEL 0x80 /* receive multiframe yellow alarm */
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#define LMC_T1F_WRITE 0
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#define LMC_T1F_READ 1
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typedef struct lmc_st1f_control {
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int command;
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int address;
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int value;
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char __user *data;
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} lmc_t1f_control;
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enum lmc_xilinx_c {
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lmc_xilinx_reset = 1,
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lmc_xilinx_load_prom = 2,
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lmc_xilinx_load = 3
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};
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struct lmc_xilinx_control {
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enum lmc_xilinx_c command;
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int len;
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char __user *data;
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};
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/* ------------------ end T1 defs ------------------- */
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#define LMC_MII_LedMask 0x0780
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#define LMC_MII_LedBitPos 7
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#endif
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