/** @file
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Copyright (c) 2011 - 2019, Intel Corporaton. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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The original software modules are licensed as follows:
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
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Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef KSZ9031_PHY_DXE_H__
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#define KSZ9031_PHY_DXE_H__
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typedef struct {
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UINT32 PhyAddr;
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UINT32 PhyCurrentLink;
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UINT32 PhyOldLink;
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} PHY_DRIVER;
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//
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// PHY Registers
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//
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#define PHY_BASIC_CTRL 0
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#define PHY_BASIC_STATUS 1
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#define PHY_ID1 2
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#define PHY_ID2 3
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#define PHY_AUTO_NEG_ADVERT 4
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#define PHY_AUTO_NEG_LINK_ABILITY 5
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#define PHY_AUTO_NEG_EXP 6
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#define PHY_1000BASE_T_CONTROL 9
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#define PHY_1000BASE_T_STATUS 10
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#define PHY_MODE 17
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#define PHY_SPECIAL_MODES 18
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#define PHY_SPECIAL_CTLR 27
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#define PHY_INT_SRC 29
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#define PHY_INT_MASK 30
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#define PHY_SPECIAL_PHY_CTLR 31
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// PHY control register bits
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#define PHYCTRL_COLL_TEST BIT7 // Collision test enable
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#define PHYCTRL_DUPLEX_MODE BIT8 // Set Duplex Mode
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#define PHYCTRL_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities
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#define PHYCTRL_PD BIT11 // Power-Down switch
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#define PHYCTRL_AUTO_EN BIT12 // Auto-Negotiation Enable
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#define PHYCTRL_SPEED_SEL BIT13 // Link Speed Selection
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#define PHYCTRL_LOOPBK BIT14 // Set loopback mode
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#define PHYCTRL_RESET BIT15 // Do a PHY reset
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// PHY status register bits
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#define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability
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#define PHYSTS_JABBER BIT1 // Jabber condition detected
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#define PHYSTS_LINK_STS BIT2 // Link Status
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#define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability
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#define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected
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#define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed
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#define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability
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#define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability
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#define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
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#define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability
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#define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
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// PHY Auto-Negotiation advertisement
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#define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector
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#define PHYANA_10BASET BIT5 // Advertise 10BASET capability
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#define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability
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#define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability
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#define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability
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#define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability
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#define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
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#define PHYLPA_SLCT 0x001f // Same as advertise selector
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#define PHYLPA_10HALF 0x0020 // Can do 10mbps half-duplex
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#define PHYLPA_1000XFULL 0x0020 // Can do 1000BASE-X full-duplex
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#define PHYLPA_10FULL 0x0040 // Can do 10mbps full-duplex
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#define PHYLPA_1000XHALF 0x0040 // Can do 1000BASE-X half-duplex
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#define PHYLPA_100HALF 0x0080 // Can do 100mbps half-duplex
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#define PHYLPA_1000XPAUSE 0x0080 // Can do 1000BASE-X pause
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#define PHYLPA_100FULL 0x0100 // Can do 100mbps full-duplex
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#define PHYLPA_1000XPAUSE_ASYM 0x0100 // Can do 1000BASE-X pause asym
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#define PHYLPA_100BASE4 0x0200 // Can do 100mbps 4k packets
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#define PHYLPA_PAUSE_CAP 0x0400 // Can pause
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#define PHYLPA_PAUSE_ASYM 0x0800 // Can pause asymetrically
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#define PHYLPA_RESV 0x1000 // Unused
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#define PHYLPA_RFAULT 0x2000 // Link partner faulted
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#define PHYLPA_LPACK 0x4000 // Link partner acked us
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#define PHYLPA_NPAGE 0x8000 // Next page bit
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#define PHYLPA_DUPLEX (LPA_10FULL | LPA_100FULL)
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#define PHYLPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
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// 1000BASE-T Status register
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#define PHYLPA_1000FULL 0x0800 // Link partner 1000BASE-T full duplex
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#define PHYLPA_1000HALF 0x0400 // Link partner 1000BASE-T half duplex
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// 1000BASE-T Control register
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#define PHYADVERTISE_1000FULL 0x0200 // Advertise 1000BASE-T full duplex
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#define PHYADVERTISE_1000HALF 0x0100 // Advertise 1000BASE-T half duplex
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#define SPEED_1000 1000
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#define SPEED_100 100
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#define SPEED_10 10
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#define DUPLEX_FULL 1
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#define DUPLEX_HALF 0
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// PHY Super Special control/status
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#define PHYSSCS_HCDSPEED_MASK (7 << 2) // Speed indication
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#define PHYSSCS_AUTODONE BIT12 // Auto-Negotiation Done
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// Flags for PHY reset
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#define PHY_RESET_PMT BIT0
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#define PHY_RESET_BCR BIT1
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#define PHY_RESET_CHECK_LINK BIT2
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// Flags for auto negotiation
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#define AUTO_NEGOTIATE_COLLISION_TEST BIT0
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#define AUTO_NEGOTIATE_ADVERTISE_ALL BIT1
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// Micrel KSZ9031 Extended registers
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#define PHY_KSZ9031RN_CONTROL_PAD_SKEW_REG 4
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#define PHY_KSZ9031RN_RX_DATA_PAD_SKEW_REG 5
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#define PHY_KSZ9031RN_TX_DATA_PAD_SKEW_REG 6
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#define PHY_KSZ9031RN_CLK_PAD_SKEW_REG 8
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// Data operations
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#define PHY_KSZ9031_MOD_DATA_NO_POST_INC 0x1
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#define PHY_KSZ9031_MOD_DATA_POST_INC_RW 0x2
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#define PHY_KSZ9031_MOD_DATA_POST_INC_W 0x3
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#define PHY_KSZ9031RN_MMD_CTRL_REG 0x0d
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#define PHY_KSZ9031RN_MMD_REGDATA_REG 0x0e
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#define PHY_KSZ9031RN_CLK_SKEW_CLR_MASK 0x3FF
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#define PHY_KSZ9031RN_CONTROL_SKEW_CLR_MASK 0xFF
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#define PHY_KSZ9031RN_RX_DATA_SKEW_CLR_MASK 0xFF
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#define PHY_KSZ9031RN_TX_DATA_SKEW_CLR_MASK 0xFF
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#define PHY_KSZ9031RN_CLK_PAD_SKEW_VALUE 0x3FC
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#define PHY_KSZ9031RN_CONTROL_PAD_SKEW_VALUE 0x70
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#define PHY_KSZ9031RN_RX_DATA_PAD_SKEW_VALUE 0x7777
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#define PHY_KSZ9031RN_TX_DATA_PAD_SKEW_VALUE 0x0
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#define PHY_KSZ9031RN_DEV_ADDR 0x2
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// MMD Address 0h, Auto-Negotiation FLP burst transmit timing
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#define PHY_KSZ9031RN_MMD_DEV_ADDR_00 0x00
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#define PHY_KSZ9031RN_MMD_D0_FLP_LO_REG 3
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#define PHY_KSZ9031RN_MMD_D0_FLP_16MS_LO 0x1A80
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#define PHY_KSZ9031RN_MMD_D0_FLP_HI_REG 4
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#define PHY_KSZ9031RN_MMD_D0_FLP_16MS_HI 0x0006
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// HPS MII
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#define MII_BUSY (1 << 0)
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#define MII_WRITE (1 << 1)
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#define MII_CLKRANGE_60_100M (0x0)
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#define MII_CLKRANGE_100_150M (0x4)
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#define MII_CLKRANGE_20_35M (0x8)
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#define MII_CLKRANGE_35_60M (0xC)
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#define MII_CLKRANGE_150_250M (0x10)
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#define MII_CLKRANGE_250_300M (0x14)
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#define MIIADDRSHIFT (11)
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#define MIIREGSHIFT (6)
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#define MII_REGMSK (0x1F << 6)
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#define MII_ADDRMSK (0x1F << 11)
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// Others
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#define PHY_INVALID_ID 0xFFFF
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#define LINK_UP 1
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#define LINK_DOWN 0
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#define PHY_TIMEOUT 200000
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EFI_STATUS
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EFIAPI
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PhyDxeInitialization (
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IN PHY_DRIVER *PhyDriver,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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PhyDetectDevice (
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IN PHY_DRIVER *PhyDriver,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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PhyConfig (
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IN PHY_DRIVER *PhyDriver,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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PhySoftReset (
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IN PHY_DRIVER *PhyDriver,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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PhyReadId (
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IN UINT32 PhyAddr,
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IN UINTN MacBaseAddress
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);
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VOID
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EFIAPI
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PhyConfigSkew (
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IN PHY_DRIVER *PhyDriver,
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IN UINTN MacBaseAddress
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);
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VOID
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EFIAPI
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PhyDisplayConfigSkew (
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IN PHY_DRIVER *PhyDriver,
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IN UINTN MacBaseAddress
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);
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VOID
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EFIAPI
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PhyConfigFlpBurstTiming (
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IN PHY_DRIVER *PhyDriver,
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IN UINTN MacBaseAddress
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);
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VOID
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EFIAPI
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PhyDisplayFlpBurstTiming (
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IN PHY_DRIVER *PhyDriver,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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PhyAutoNego (
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IN PHY_DRIVER *PhyDriver,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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PhyLinkAdjustEmacConfig (
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IN PHY_DRIVER *PhyDriver,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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PhyCheckLinkStatus (
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IN PHY_DRIVER *PhyDriver,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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PhyReadCapability (
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IN PHY_DRIVER *PhyDriver,
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IN UINT32 *Speed,
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IN UINT32 *Duplex,
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IN UINTN MacBaseAddress
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);
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VOID
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EFIAPI
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PhyDisplayAbility (
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IN UINT32 Speed,
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IN UINT32 Duplex
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);
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EFI_STATUS
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EFIAPI
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PhyRead (
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IN UINT32 Addr,
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IN UINT32 Reg,
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OUT UINT32 *Data,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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PhyWrite (
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IN UINT32 Addr,
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IN UINT32 Reg,
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IN UINT32 Data,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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Phy9031ExtendedWrite (
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IN PHY_DRIVER *PhyDriver,
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IN UINT32 Mode,
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IN UINT32 DevAddr,
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IN UINT32 Regnum,
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IN UINT16 Val,
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IN UINTN MacBaseAddress
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);
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UINT32
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EFIAPI
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Phy9031ExtendedRead (
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IN PHY_DRIVER *PhyDriver,
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IN UINT32 Mode,
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IN UINT32 DevAddr,
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IN UINT32 Regnum,
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IN UINTN MacBaseAddress
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);
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#endif /* KSZ9031_PHY_DXE_H__ */
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