/** @file
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Copyright (c) 2011 - 2019, Intel Corporaton. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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The original software modules are licensed as follows:
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Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
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Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "EmacDxeUtil.h"
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#include "PhyDxeUtil.h"
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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VOID
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EFIAPI
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EmacSetMacAddress (
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IN EFI_MAC_ADDRESS *MacAddress,
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IN UINTN MacBaseAddress
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)
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{
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DEBUG ((DEBUG_INFO, "SNP:MAC: %a ()\r\n", __FUNCTION__));
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// Note: This MAC_ADDR0 registers programming sequence cannot be swap:
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// Must program HIGH Offset first before LOW Offset
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// because synchronization is triggered when MAC Address0 Low Register are written.
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MmioWrite32 (MacBaseAddress + DW_EMAC_GMACGRP_MAC_ADDRESS0_HIGH_OFST,
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(UINT32)(MacAddress->Addr[4] & 0xFF) |
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((MacAddress->Addr[5] & 0xFF) << 8)
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);
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// MacAddress->Addr[0,1,2] is the 3 bytes OUI
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MmioWrite32 (MacBaseAddress + DW_EMAC_GMACGRP_MAC_ADDRESS0_LOW_OFST,
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(MacAddress->Addr[0] & 0xFF) |
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((MacAddress->Addr[1] & 0xFF) << 8) |
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((MacAddress->Addr[2] & 0xFF) << 16) |
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((MacAddress->Addr[3] & 0xFF) << 24)
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);
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DEBUG ((DEBUG_INFO, "SNP:MAC: gmacgrp_mac_address0_low = 0x%08X \r\n",
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MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_MAC_ADDRESS0_LOW_OFST)));
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DEBUG ((DEBUG_INFO, "SNP:MAC: gmacgrp_mac_address0_high = 0x%08X \r\n",
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MmioRead32 (MacBaseAddress +DW_EMAC_GMACGRP_MAC_ADDRESS0_HIGH_OFST)));
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}
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VOID
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EFIAPI
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EmacReadMacAddress (
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OUT EFI_MAC_ADDRESS *MacAddress,
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IN UINTN MacBaseAddress
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)
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{
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UINT32 MacAddrHighValue;
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UINT32 MacAddrLowValue;
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DEBUG ((DEBUG_INFO, "SNP:MAC: %a ()\r\n", __FUNCTION__));
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// Read the Mac Addr high register
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MacAddrHighValue = (MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_MAC_ADDRESS0_HIGH_OFST) & 0xFFFF);
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// Read the Mac Addr low register
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MacAddrLowValue = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_MAC_ADDRESS0_LOW_OFST);
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SetMem (MacAddress, sizeof(*MacAddress), 0);
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MacAddress->Addr[0] = (MacAddrLowValue & 0xFF);
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MacAddress->Addr[1] = (MacAddrLowValue & 0xFF00) >> 8;
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MacAddress->Addr[2] = (MacAddrLowValue & 0xFF0000) >> 16;
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MacAddress->Addr[3] = (MacAddrLowValue & 0xFF000000) >> 24;
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MacAddress->Addr[4] = (MacAddrHighValue & 0xFF);
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MacAddress->Addr[5] = (MacAddrHighValue & 0xFF00) >> 8;
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DEBUG ((DEBUG_INFO, "SNP:MAC: MAC Address = %02X:%02X:%02X:%02X:%02X:%02X\r\n",
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MacAddress->Addr[0], MacAddress->Addr[1], MacAddress->Addr[2],
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MacAddress->Addr[3], MacAddress->Addr[4], MacAddress->Addr[5]
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));
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}
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EFI_STATUS
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EFIAPI
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EmacDxeInitialization (
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IN EMAC_DRIVER *EmacDriver,
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IN UINTN MacBaseAddress
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)
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{
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DEBUG ((DEBUG_INFO, "SNP:MAC: %a ()\r\n", __FUNCTION__));
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// Init EMAC DMA
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EmacDmaInit (EmacDriver, MacBaseAddress);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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EmacDmaInit (
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IN EMAC_DRIVER *EmacDriver,
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IN UINTN MacBaseAddress
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)
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{
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UINT32 DmaConf;
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UINT32 DmaOpmode;
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UINT32 InterruptEnable;
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DEBUG ((DEBUG_INFO, "SNP:MAC: %a ()\r\n", __FUNCTION__));
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// This section provides the instructions for initializing the DMA registers in the proper sequence. This
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// initialization sequence can be done after the EMAC interface initialization has been completed. Perform
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// the following steps to initialize the DMA:
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// 1. Provide a software reset to reset all of the EMAC internal registers and logic. (DMA Register 0 (Bus
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// Mode Register) � bit 0).
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MmioOr32 (MacBaseAddress +
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DW_EMAC_DMAGRP_BUS_MODE_OFST,
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DW_EMAC_DMAGRP_BUS_MODE_SWR_SET_MSK);
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// 2. Wait for the completion of the reset process (poll bit 0 of the DMA Register 0 (Bus Mode Register),
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// which is only cleared after the reset operation is completed).
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while (DW_EMAC_DMAGRP_BUS_MODE_SWR_GET (MmioRead32 (MacBaseAddress + DW_EMAC_DMAGRP_BUS_MODE_OFST)));
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// 3. Poll the bits of Register 11 (AHB or AXI Status) to confirm that all previously initiated (before
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// software reset) or ongoing transactions are complete.
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// Note: If the application cannot poll the register after soft reset (because of performance reasons), then
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// it is recommended that you continue with the next steps and check this register again (as
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// mentioned in 12 on page 1-72) before triggering the DMA operations.�
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// 4. Program the following fields to initialize the Bus Mode Register by setting values in DMA Register 0
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// (Bus Mode Register):
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// � Mixed Burst and AAL
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// � Fixed burst or undefined burst
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// � Burst length values and burst mode values
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// � Descriptor Length (only valid if Ring Mode is used)
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// � TX and RX DMA Arbitration scheme
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// 5. Program the interface options in Register 10 (AXI Bus Mode Register). If fixed burst-length is enabled,
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// then select the maximum burst-length possible on the bus (bits[7:1]).�
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DmaConf = DW_EMAC_DMAGRP_BUS_MODE_FB_SET_MSK | DW_EMAC_DMAGRP_BUS_MODE_PBL_SET_MSK | DW_EMAC_DMAGRP_BUS_MODE_PR_SET_MSK;
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MmioOr32 (MacBaseAddress +
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DW_EMAC_DMAGRP_BUS_MODE_OFST,
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DmaConf);
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// 6. Create a proper descriptor chain for transmit and receive. In addition, ensure that the receive descriptors
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// are owned by DMA (bit 31 of descriptor should be set). When OSF mode is used, at least two
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// descriptors are required.
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// 7. Make sure that your software creates three or more different transmit or receive descriptors in the
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// chain before reusing any of the descriptors.
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// 8. Initialize receive and transmit descriptor list address with the base address of the transmit and receive
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// descriptor (Register 3 (Receive Descriptor List Address Register) and Register 4 (Transmit Descriptor
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// List Address Register) respectively).
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EmacSetupTxdesc (EmacDriver, MacBaseAddress);
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EmacSetupRxdesc (EmacDriver, MacBaseAddress);
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// 9. Program the following fields to initialize the mode of operation in Register 6 (Operation Mode
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// Register):
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// � Receive and Transmit Store And Forward�
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// � Receive and Transmit Threshold Control (RTC and TTC)�
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// � Hardware Flow Control enable�
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// � Flow Control Activation and De-activation thresholds for MTL Receive and Transmit FIFO buffers
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// (RFA and RFD)�
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// � Error frame and undersized good frame forwarding enable�
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// � OSF Mode�
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DmaOpmode = DW_EMAC_DMAGRP_OPERATION_MODE_FTF_SET_MSK | DW_EMAC_DMAGRP_OPERATION_MODE_TSF_SET_MSK;
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MmioOr32 (MacBaseAddress +
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DW_EMAC_DMAGRP_OPERATION_MODE_OFST,
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DmaOpmode);
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//while (DW_EMAC_DMAGRP_OPERATION_MODE_FTF_GET (MmioRead32 (MacBaseAddress + DW_EMAC_DMAGRP_OPERATION_MODE_OFST)));
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// 10.Clear the interrupt requests, by writing to those bits of the status register (interrupt bits only) that are
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// set. For example, by writing 1 into bit 16, the normal interrupt summary clears this bit (DMA Register 5 (Status Register)).
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MmioOr32 (MacBaseAddress +
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DW_EMAC_DMAGRP_STATUS_OFST,
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0x1FFFF);
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// 11.Enable the interrupts by programming Register 7 (Interrupt Enable Register).
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InterruptEnable = DW_EMAC_DMAGRP_INTERRUPT_ENABLE_TIE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_RIE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_NIE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_AIE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_FBE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_UNE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_TSE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_TUE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_TJE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_OVE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_RUE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_RSE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_RWE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_ETE_SET_MSK |
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_ERE_SET_MSK;
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MmioWrite32 (MacBaseAddress +
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DW_EMAC_DMAGRP_INTERRUPT_ENABLE_OFST,
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InterruptEnable);
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// 12.Read Register 11 (AHB or AXI Status) to confirm that all previous transactions are complete.�
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// Note: If any previous transaction is still in progress when you read the Register 11 (AHB or AXI
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// Status), then it is strongly recommended to check the slave components addressed by the
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// master interface.
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if (MmioRead32 (MacBaseAddress + DW_EMAC_DMAGRP_AHB_OR_AXI_STATUS_OFST) != 0) {
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DEBUG ((DEBUG_INFO, "SNP:MAC: Error! Previous AXI transaction is still in progress\r\n"));
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//check the slave components addressed by the master interface
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return EFI_DEVICE_ERROR;
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}
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DmaOpmode = DW_EMAC_DMAGRP_OPERATION_MODE_ST_SET_MSK | DW_EMAC_DMAGRP_OPERATION_MODE_SR_SET_MSK;
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MmioOr32 (MacBaseAddress +
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DW_EMAC_DMAGRP_OPERATION_MODE_OFST,
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DmaOpmode);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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EmacSetupTxdesc (
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IN EMAC_DRIVER *EmacDriver,
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IN UINTN MacBaseAddress
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)
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{
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INTN Index;
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DESIGNWARE_HW_DESCRIPTOR *TxDescriptor;
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for (Index = 0; Index < CONFIG_TX_DESCR_NUM; Index++) {
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TxDescriptor = (VOID *)(UINTN)EmacDriver->TxdescRingMap[Index].AddrMap;
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TxDescriptor->Addr = (UINT32)(UINTN)&EmacDriver->TxBuffer[Index * CONFIG_ETH_BUFSIZE];
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if (Index < 9) {
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TxDescriptor->AddrNext = (UINT32)(UINTN)EmacDriver->TxdescRingMap[Index + 1].AddrMap;
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}
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TxDescriptor->Tdes0 = TDES0_TXCHAIN;
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TxDescriptor->Tdes1 = 0;
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}
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// Correcting the last pointer of the chain
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TxDescriptor->AddrNext = (UINT32)(UINTN)EmacDriver->TxdescRingMap[0].AddrMap;
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// Write the address of tx descriptor list
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MmioWrite32 (MacBaseAddress +
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DW_EMAC_DMAGRP_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_OFST,
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(UINT32)(UINTN)EmacDriver->TxdescRingMap[0].AddrMap);
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// Initialize the descriptor number
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EmacDriver->TxCurrentDescriptorNum = 0;
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EmacDriver->TxNextDescriptorNum = 0;
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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EmacSetupRxdesc (
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IN EMAC_DRIVER *EmacDriver,
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IN UINTN MacBaseAddress
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)
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{
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INTN Index;
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DESIGNWARE_HW_DESCRIPTOR *RxDescriptor;
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for (Index = 0; Index < CONFIG_RX_DESCR_NUM; Index++) {
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RxDescriptor = (VOID *)(UINTN)EmacDriver->RxdescRingMap[Index].AddrMap;
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RxDescriptor->Addr = EmacDriver->RxBufNum[Index].AddrMap;
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if (Index < 9) {
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RxDescriptor->AddrNext = (UINT32)(UINTN)EmacDriver->RxdescRingMap[Index + 1].AddrMap;
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}
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RxDescriptor->Tdes0 = RDES0_OWN;
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RxDescriptor->Tdes1 = RDES1_CHAINED | RX_MAX_PACKET;
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}
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// Correcting the last pointer of the chain
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RxDescriptor->AddrNext = (UINT32)(UINTN)EmacDriver->RxdescRingMap[0].AddrMap;
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// Write the address of tx descriptor list
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MmioWrite32(MacBaseAddress +
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DW_EMAC_DMAGRP_RECEIVE_DESCRIPTOR_LIST_ADDRESS_OFST,
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(UINT32)(UINTN)EmacDriver->RxdescRingMap[0].AddrMap);
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// Initialize the descriptor number
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EmacDriver->RxCurrentDescriptorNum = 0;
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EmacDriver->RxNextDescriptorNum = 0;
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return EFI_SUCCESS;
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}
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VOID
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EFIAPI
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EmacStartTransmission (
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IN UINTN MacBaseAddress
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)
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{
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DEBUG ((DEBUG_INFO, "SNP:MAC: %a ()\r\n", __FUNCTION__));
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MmioOr32 (MacBaseAddress +
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DW_EMAC_GMACGRP_MAC_CONFIGURATION_OFST,
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DW_EMAC_GMACGRP_MAC_CONFIGURATION_RE_SET_MSK |
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DW_EMAC_GMACGRP_MAC_CONFIGURATION_TE_SET_MSK
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);
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}
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EFI_STATUS
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EFIAPI
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EmacRxFilters (
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IN UINT32 ReceiveFilterSetting,
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IN BOOLEAN Reset,
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IN UINTN NumMfilter OPTIONAL,
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IN EFI_MAC_ADDRESS *Mfilter OPTIONAL,
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IN UINTN MacBaseAddress
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)
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{
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UINT32 MacFilter;
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UINT32 Crc;
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UINT32 Count;
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UINT32 HashReg;
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UINT32 HashBit;
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UINT32 Reg;
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UINT32 Val;
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// If reset then clear the filter registers
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if (Reset) {
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for (Count = 0; Count < NumMfilter; Count++)
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{
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MmioWrite32 (MacBaseAddress + HASH_TABLE_REG(Count), 0x00000000);
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}
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}
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// Set MacFilter to the reset value of the DW_EMAC_GMACGRP_MAC_FRAME_FILTER register.
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MacFilter = DW_EMAC_GMACGRP_MAC_FRAME_FILTER_RESET;
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if (ReceiveFilterSetting & EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST) {
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MacFilter |= DW_EMAC_GMACGRP_MAC_FRAME_FILTER_HMC_SET_MSK;
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// Set the hash tables
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if ((NumMfilter > 0) && (!Reset)) {
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// Go through each filter address and set appropriate bits on hash table
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for (Count = 0; Count < NumMfilter; Count++) {
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// Generate a 32-bit CRC
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Crc = GenEtherCrc32 (&Mfilter[Count], 6);
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// reserve CRC + take upper 8 bit = take lower 8 bit and reverse it
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Val = BitReverse(Crc & 0xff);
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// The most significant bits determines the register to be used (Hash Table Register X),
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// and the least significant five bits determine the bit within the register.
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// For example, a hash value of 8b'10111111 selects Bit 31 of the Hash Table Register 5.
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HashReg = (Val >> 5);
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HashBit = (Val & 0x1f);
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Reg = MmioRead32 (MacBaseAddress + HASH_TABLE_REG(HashReg));
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// set 1 to HashBit of HashReg
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// for example, set 1 to bit 31 to Reg 5 as in above example
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Reg |= (1 << HashBit);
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MmioWrite32(MacBaseAddress + HASH_TABLE_REG(HashReg), Reg);
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}
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}
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}
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if ((ReceiveFilterSetting & EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST) == 0) {
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MacFilter |= DW_EMAC_GMACGRP_MAC_FRAME_FILTER_DBF_SET_MSK;
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}
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if (ReceiveFilterSetting & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS) {
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MacFilter |= DW_EMAC_GMACGRP_MAC_FRAME_FILTER_PR_SET_MSK;
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}
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if (ReceiveFilterSetting & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST) {
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MacFilter |= ( DW_EMAC_GMACGRP_MAC_FRAME_FILTER_PM_SET_MSK);
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}
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// Set MacFilter to EMAC register
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MmioWrite32 (MacBaseAddress + DW_EMAC_GMACGRP_MAC_FRAME_FILTER_OFST, MacFilter);
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return EFI_SUCCESS;
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}
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UINT32
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EFIAPI
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GenEtherCrc32 (
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IN EFI_MAC_ADDRESS *Mac,
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IN UINT32 AddrLen
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)
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{
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INT32 Iter;
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UINT32 Remainder;
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UINT8 *Ptr;
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Iter = 0;
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Remainder = 0xFFFFFFFF; // 0xFFFFFFFF is standard seed for Ethernet
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// Convert Mac Address to array of bytes
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Ptr = (UINT8 *)Mac;
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// Generate the Crc bit-by-bit (LSB first)
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while (AddrLen--) {
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Remainder ^= *Ptr++;
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for (Iter = 0; Iter < 8; Iter++) {
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// Check if exponent is set
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if (Remainder & 1) {
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Remainder = (Remainder >> 1) ^ CRC_POLYNOMIAL;
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} else {
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Remainder = (Remainder >> 1) ^ 0;
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}
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}
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}
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return (~Remainder);
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}
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STATIC CONST UINT8 NibbleTab[] = {
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/* 0x0 0000 -> 0000 */ 0x0,
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/* 0x1 0001 -> 1000 */ 0x8,
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/* 0x2 0010 -> 0100 */ 0x4,
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/* 0x3 0011 -> 1100 */ 0xc,
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/* 0x4 0100 -> 0010 */ 0x2,
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/* 0x5 0101 -> 1010 */ 0xa,
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/* 0x6 0110 -> 0110 */ 0x6,
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/* 0x7 0111 -> 1110 */ 0xe,
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/* 0x8 1000 -> 0001 */ 0x1,
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/* 0x9 1001 -> 1001 */ 0x9,
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/* 0xa 1010 -> 0101 */ 0x5,
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/* 0xb 1011 -> 1101 */ 0xd,
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/* 0xc 1100 -> 0011 */ 0x3,
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/* 0xd 1101 -> 1011 */ 0xb,
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/* 0xe 1110 -> 0111 */ 0x7,
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/* 0xf 1111 -> 1111 */ 0xf
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};
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UINT8
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EFIAPI
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BitReverse (
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UINT8 Value
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)
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{
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return (NibbleTab[Value & 0xf] << 4) | NibbleTab[Value >> 4];
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}
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VOID
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EFIAPI
|
EmacStopTxRx (
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IN UINTN MacBaseAddress
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)
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{
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DEBUG ((DEBUG_INFO, "SNP:MAC: %a ()\r\n", __FUNCTION__));
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// Stop DMA TX
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MmioAnd32 (MacBaseAddress +
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DW_EMAC_DMAGRP_OPERATION_MODE_OFST,
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DW_EMAC_DMAGRP_OPERATION_MODE_ST_CLR_MSK);
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// Flush TX
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MmioOr32 (MacBaseAddress +
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DW_EMAC_DMAGRP_OPERATION_MODE_OFST,
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DW_EMAC_DMAGRP_OPERATION_MODE_FTF_SET_MSK);
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// Stop transmitters
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MmioAnd32 (MacBaseAddress +
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DW_EMAC_GMACGRP_MAC_CONFIGURATION_OFST,
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DW_EMAC_GMACGRP_MAC_CONFIGURATION_RE_CLR_MSK &
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DW_EMAC_GMACGRP_MAC_CONFIGURATION_TE_CLR_MSK);
|
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// Stop DMA RX
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MmioAnd32 (MacBaseAddress +
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DW_EMAC_DMAGRP_OPERATION_MODE_OFST,
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DW_EMAC_DMAGRP_OPERATION_MODE_SR_CLR_MSK);
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}
|
|
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EFI_STATUS
|
EFIAPI
|
EmacDmaStart (
|
IN UINTN MacBaseAddress
|
)
|
{
|
// Start the transmission
|
MmioWrite32(MacBaseAddress +
|
DW_EMAC_DMAGRP_TRANSMIT_POLL_DEMAND_OFST,
|
0x1);
|
return EFI_SUCCESS;
|
}
|
|
|
VOID
|
EFIAPI
|
EmacGetDmaStatus (
|
OUT UINT32 *IrqStat OPTIONAL,
|
IN UINTN MacBaseAddress
|
)
|
{
|
UINT32 DmaStatus;
|
UINT32 ErrorBit;
|
UINT32 Mask = 0;
|
|
DmaStatus = MmioRead32 (MacBaseAddress +
|
DW_EMAC_DMAGRP_STATUS_OFST);
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_NIS_SET_MSK) {
|
Mask |= DW_EMAC_DMAGRP_STATUS_NIS_SET_MSK;
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// Rx interrupt
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_RI_SET_MSK) {
|
*IrqStat |= EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
|
Mask |= DW_EMAC_DMAGRP_STATUS_RI_SET_MSK;
|
} else {
|
*IrqStat &= ~EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
|
}
|
// Tx interrupt
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_TI_SET_MSK) {
|
*IrqStat |= EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;
|
Mask |= DW_EMAC_DMAGRP_STATUS_TI_SET_MSK;
|
} else {
|
*IrqStat &= ~EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;
|
}
|
// Tx Buffer
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_TU_SET_MSK){
|
Mask |= DW_EMAC_DMAGRP_STATUS_TU_SET_MSK;
|
}
|
// Early receive interrupt
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_ERI_SET_MSK) {
|
Mask |= DW_EMAC_DMAGRP_STATUS_ERI_SET_MSK;
|
}
|
}
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_AIS_SET_MSK) {
|
Mask |= DW_EMAC_DMAGRP_STATUS_AIS_SET_MSK;
|
// Transmit process stop
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_TPS_SET_MSK) {
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Transmit process stop\n"));
|
Mask |= DW_EMAC_DMAGRP_STATUS_TPS_SET_MSK;
|
}
|
// Transmit jabber timeout
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_TJT_SET_MSK) {
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Transmit jabber timeout\n"));
|
Mask |= DW_EMAC_DMAGRP_STATUS_TJT_SET_MSK;
|
}
|
// Receive FIFO overflow
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_OVF_SET_MSK) {
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Receive FIFO overflow\n"));
|
Mask |= DW_EMAC_DMAGRP_STATUS_OVF_SET_MSK;
|
}
|
// Transmit FIFO underflow
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_UNF_SET_MSK) {
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Receive FIFO underflow\n"));
|
Mask |= DW_EMAC_DMAGRP_STATUS_UNF_SET_MSK;
|
}
|
// Receive buffer unavailable
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_RU_SET_MSK) {
|
Mask |= DW_EMAC_DMAGRP_STATUS_RU_SET_MSK;
|
}
|
|
// Receive process stop
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_RPS_SET_MSK) {
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Receive process stop\n"));
|
Mask |= DW_EMAC_DMAGRP_STATUS_RPS_SET_MSK;
|
}
|
// Receive watchdog timeout
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_RWT_SET_MSK) {
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Receive watchdog timeout\n"));
|
Mask |= DW_EMAC_DMAGRP_STATUS_RWT_SET_MSK;
|
}
|
// Early transmit interrupt
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_ETI_SET_MSK) {
|
Mask |= DW_EMAC_DMAGRP_STATUS_ETI_SET_MSK;
|
}
|
// Fatal bus error
|
if (DmaStatus & DW_EMAC_DMAGRP_STATUS_FBI_SET_MSK) {
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Fatal bus error:\n"));
|
Mask |= DW_EMAC_DMAGRP_STATUS_FBI_SET_MSK;
|
|
ErrorBit = DW_EMAC_DMAGRP_STATUS_EB_GET (DmaStatus);
|
switch (ErrorBit) {
|
case RX_DMA_WRITE_DATA_TRANSFER_ERROR:
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Rx Dma write data transfer error\n"));
|
break;
|
case TX_DMA_READ_DATA_TRANSFER_ERROR:
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Tx Dma read data transfer error\n"));
|
break;
|
case RX_DMA_DESCRIPTOR_WRITE_ACCESS_ERROR:
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Rx Dma descriptor write access error\n"));
|
break;
|
case RX_DMA_DESCRIPTOR_READ_ACCESS_ERROR:
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Rx Dma descriptor read access error\n"));
|
break;
|
case TX_DMA_DESCRIPTOR_WRITE_ACCESS_ERROR:
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Tx Dma descriptor write access error\n"));
|
break;
|
case TX_DMA_DESCRIPTOR_READ_ACCESS_ERROR:
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Tx Dma descriptor read access error\n"));
|
break;
|
default:
|
DEBUG ((DEBUG_INFO, "SNP:MAC: Undefined error\n"));
|
break;
|
}
|
}
|
}
|
MmioOr32 (MacBaseAddress +
|
DW_EMAC_DMAGRP_STATUS_OFST,
|
Mask);
|
}
|
|
|
VOID
|
EFIAPI
|
EmacGetStatistic (
|
OUT EFI_NETWORK_STATISTICS *Statistic,
|
IN UINTN MacBaseAddress
|
)
|
{
|
EFI_NETWORK_STATISTICS *Stats;
|
|
DEBUG ((DEBUG_INFO, "SNP:MAC: %a ()\r\n", __FUNCTION__));
|
|
// Allocate Resources
|
Stats = AllocateZeroPool (sizeof (EFI_NETWORK_STATISTICS));
|
if (Stats == NULL) {
|
return;
|
}
|
|
Stats->RxTotalFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_RXFRAMECOUNT_GB_OFST);
|
Stats->RxUndersizeFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_RXUNDERSIZE_G_OFST);
|
Stats->RxOversizeFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_RXOVERSIZE_G_OFST);
|
Stats->RxUnicastFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_RXUNICASTFRAMES_G_OFST);
|
Stats->RxBroadcastFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_RXBROADCASTFRAMES_G_OFST);
|
Stats->RxMulticastFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_RXMULTICASTFRAMES_G_OFST);
|
Stats->RxCrcErrorFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_RXCRCERROR_OFST);
|
Stats->RxTotalBytes = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_RXOCTETCOUNT_GB_OFST);
|
Stats->RxGoodFrames = Stats->RxUnicastFrames + Stats->RxBroadcastFrames + Stats->RxMulticastFrames;
|
|
Stats->TxTotalFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_TXFRAMECOUNT_GB_OFST);
|
Stats->TxGoodFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_TXFRAMECOUNT_G_OFST);
|
Stats->TxOversizeFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_TXOVERSIZE_G_OFST);
|
Stats->TxUnicastFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_TXUNICASTFRAMES_GB_OFST);
|
Stats->TxBroadcastFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_TXBROADCASTFRAMES_G_OFST);
|
Stats->TxMulticastFrames = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_TXMULTICASTFRAMES_G_OFST);
|
Stats->TxTotalBytes = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_TXOCTETCOUNT_GB_OFST);
|
Stats->Collisions = MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_TXLATECOL_OFST) +
|
MmioRead32 (MacBaseAddress + DW_EMAC_GMACGRP_TXEXESSCOL_OFST);
|
|
// Fill in the statistics
|
CopyMem (Statistic, Stats, sizeof (EFI_NETWORK_STATISTICS));
|
}
|
|
|
VOID
|
EFIAPI
|
EmacConfigAdjust (
|
IN UINT32 Speed,
|
IN UINT32 Duplex,
|
IN UINTN MacBaseAddress
|
)
|
{
|
UINT32 Config;
|
|
Config = 0;
|
if (Speed != SPEED_1000) {
|
Config |= DW_EMAC_GMACGRP_MAC_CONFIGURATION_PS_SET_MSK;
|
}
|
if (Speed == SPEED_100) {
|
Config |= DW_EMAC_GMACGRP_MAC_CONFIGURATION_FES_SET_MSK;
|
}
|
if (Duplex == DUPLEX_FULL) {
|
Config |= DW_EMAC_GMACGRP_MAC_CONFIGURATION_DM_SET_MSK;
|
}
|
MmioOr32 (MacBaseAddress +
|
DW_EMAC_GMACGRP_MAC_CONFIGURATION_OFST,
|
DW_EMAC_GMACGRP_MAC_CONFIGURATION_BE_SET_MSK |
|
DW_EMAC_GMACGRP_MAC_CONFIGURATION_DO_SET_MSK |
|
Config);
|
|
}
|
