/** @file
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Physical memory map for SynQuacer
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Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SYNQUACER_PLATFORM_MEMORYMAP_H_
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#define _SYNQUACER_PLATFORM_MEMORYMAP_H_
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// Memory mapped SPI NOR
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#define SYNQUACER_SPI_NOR_BASE 0x08000000
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#define SYNQUACER_SPI_NOR_SIZE SIZE_128MB
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// On-Chip non-secure ROM
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#define SYNQUACER_NON_SECURE_ROM_BASE 0x1F000000
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#define SYNQUACER_NON_SECURE_ROM_SZ SIZE_512KB
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// On-Chip Peripherals
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#define SYNQUACER_PERIPHERALS_BASE 0x20000000
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#define SYNQUACER_PERIPHERALS_SZ 0x0E000000
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// On-Chip non-secure SRAM
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#define SYNQUACER_NON_SECURE_SRAM_BASE 0x2E000000
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#define SYNQUACER_NON_SECURE_SRAM_SZ SIZE_64KB
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// GIC-500
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#define SYNQUACER_GIC500_DIST_BASE FixedPcdGet64 (PcdGicDistributorBase)
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#define SYNQUACER_GIC500_DIST_SIZE SIZE_256KB
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#define SYNQUACER_GIC500_RDIST_BASE FixedPcdGet64 (PcdGicRedistributorsBase)
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#define SYNQUACER_GIC500_RDIST_SIZE SIZE_8MB
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// GPIO block
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#define SYNQUACER_GPIO_BASE 0x51000000
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#define SYNQUACER_GPIO_SIZE SIZE_4KB
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// EXIU interrupt controller
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#define SYNQUACER_EXIU_BASE 0x510c0000
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#define SYNQUACER_EXIU_SIZE 0x20
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// I2C0 block
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#define SYNQUACER_I2C0_BASE 0x51200000
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#define SYNQUACER_I2C0_SIZE SIZE_4KB
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// I2C1 block
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#define SYNQUACER_I2C1_BASE 0x51210000
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#define SYNQUACER_I2C1_SIZE SIZE_4KB
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// eMMC(SDH30)
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#define SYNQUACER_EMMC_BASE 0x52300000
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#define SYNQUACER_EMMC_BASE_SZ SIZE_4KB
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#define SYNQUACER_EEPROM_BASE 0x10000000
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#define SYNQUACER_EEPROM_BASE_SZ SIZE_64KB
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// NETSEC
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#define SYNQUACER_NETSEC1_BASE 0x522D0000
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#define SYNQUACER_NETSEC1_BASE_SZ SIZE_64KB
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// PCI
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#define SYNQUACER_PCIE_BASE 0x58200000
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#define SYNQUACER_PCIE_SIZE 0x00200000
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// SCB SMMU
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#define SYNQUACER_SCB_SMMU_BASE 0x52E00000
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#define SYNQUACER_SCB_SMMU_SIZE SIZE_64KB
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#define SYNQUACER_MMIO_TIMER_CTL_BASE 0x2A810000
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#define SYNQUACER_MMIO_TIMER_CNT_BASE0 0x2A830000
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// PL011 UART
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#define SYNQUACER_UART0_BASE 0x2A400000
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#define SYNQUACER_UART0_SIZE SIZE_4KB
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// DesignWare FUART
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#define SYNQUACER_UART1_BASE 0x51040000
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#define SYNQUACER_UART1_SIZE SIZE_4KB
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// SPI controller #1
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#define SYNQUACER_SPI1_BASE 0x54810000
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#define SYNQUACER_SPI1_SIZE SIZE_4KB
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// SPI controller #1 MMIO Region
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#define SYNQUACER_SPI1_MMIO_BASE 0x10000000
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#define SYNQUACER_SPI1_MMIO_SIZE SIZE_1MB
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#endif
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