/** @file NorFlashDxe.h
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Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
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Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __NOR_FLASH_DXE_H__
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#define __NOR_FLASH_DXE_H__
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#include <PiDxe.h>
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#include <Guid/EventGroup.h>
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#include <Protocol/BlockIo.h>
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#include <Protocol/DiskIo.h>
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#include <Protocol/FirmwareVolumeBlock.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/NorFlashPlatformLib.h>
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#include "Fip006Reg.h"
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#define NOR_FLASH_ERASE_RETRY 10
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#define GET_NOR_BLOCK_ADDRESS(BaseAddr, Lba, LbaSize) \
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((BaseAddr) + (UINTN)((Lba) * (LbaSize)))
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#define NOR_FLASH_SIGNATURE SIGNATURE_32('S', 'n', 'o', 'r')
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#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, \
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NOR_FLASH_SIGNATURE)
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#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol,\
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NOR_FLASH_SIGNATURE)
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#define INSTANCE_FROM_DISKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, DiskIoProtocol, \
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NOR_FLASH_SIGNATURE)
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#define CSDC(Data, Cont, Trp, Dec) \
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(((Data) << 8) | (((Cont) & 1) << 3) | (((Trp) & 3) << 1) | ((Dec) & 1))
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#define CSDC_TRP_MBM 0
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#define CSDC_TRP_DUAL 1
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#define CSDC_TRP_QUAD 2
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#define CSDC_TRP_SINGLE 3
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#define CSDC_DEC_LEAVE_ASIS 0
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#define CSDC_DEC_DECODE 1
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#define CSDC_CONT_NON_CONTINUOUS 0
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#define CSDC_CONT_CONTINUOUS 1
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#define CSDC_ADDRESS_7_0 0x0
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#define CSDC_ADDRESS_15_8 0x1
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#define CSDC_ADDRESS_23_16 0x2
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#define CSDC_ADDRESS_31_24 0x3
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#define CSDC_HIGH_Z 0x4
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#define CSDC_END 0x7
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typedef struct {
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UINT8 Code;
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BOOLEAN AddrAccess;
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BOOLEAN AddrMode4Byte;
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BOOLEAN HighZ;
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BOOLEAN ReadWrite;
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UINT8 CscfgMbm;
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UINT8 CsdcTrp;
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} CSDC_DEFINITION;
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typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
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typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);
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#pragma pack(1)
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typedef struct {
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VENDOR_DEVICE_PATH Vendor;
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UINT8 Index;
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EFI_DEVICE_PATH_PROTOCOL End;
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} NOR_FLASH_DEVICE_PATH;
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#pragma pack()
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struct _NOR_FLASH_INSTANCE {
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UINT32 Signature;
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EFI_HANDLE Handle;
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BOOLEAN Initialized;
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NOR_FLASH_INITIALIZE Initialize;
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UINTN HostRegisterBaseAddress;
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UINTN DeviceBaseAddress;
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UINTN RegionBaseAddress;
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UINTN Size;
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UINTN BlockSize;
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UINTN LastBlock;
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EFI_LBA StartLba;
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EFI_LBA OffsetLba;
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EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
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VOID* ShadowBuffer;
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NOR_FLASH_DEVICE_PATH DevicePath;
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UINT32 Flags;
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#define NOR_FLASH_POLL_FSR BIT0
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};
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typedef struct {
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EFI_TPL OriginalTPL;
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BOOLEAN InterruptsEnabled;
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} NOR_FLASH_LOCK_CONTEXT;
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VOID
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EFIAPI
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NorFlashLock (
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NOR_FLASH_LOCK_CONTEXT *Context
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);
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VOID
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EFIAPI
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NorFlashUnlock (
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NOR_FLASH_LOCK_CONTEXT *Context
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);
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EFI_STATUS
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NorFlashReadCfiData (
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IN UINTN DeviceBaseAddress,
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IN UINTN CFI_Offset,
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IN UINT32 NumberOfBytes,
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OUT UINT32 *Data
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);
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EFI_STATUS
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NorFlashWriteBuffer (
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IN NOR_FLASH_INSTANCE *Instance,
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IN UINTN TargetAddress,
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IN UINTN BufferSizeInBytes,
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IN UINT32 *Buffer
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);
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extern UINTN mFlashNvStorageVariableBase;
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EFI_STATUS
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NorFlashCreateInstance (
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IN UINTN HostRegisterBase,
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IN UINTN NorFlashDeviceBase,
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IN UINTN NorFlashRegionBase,
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IN UINTN NorFlashSize,
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IN UINT32 Index,
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IN UINT32 BlockSize,
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IN BOOLEAN HasVarStore,
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OUT NOR_FLASH_INSTANCE** NorFlashInstance
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);
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EFI_STATUS
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EFIAPI
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NorFlashFvbInitialize (
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IN NOR_FLASH_INSTANCE* Instance
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);
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EFI_STATUS
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ValidateFvHeader (
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IN NOR_FLASH_INSTANCE *Instance
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);
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EFI_STATUS
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InitializeFvAndVariableStoreHeaders (
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IN NOR_FLASH_INSTANCE *Instance
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);
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EFI_STATUS
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EFIAPI
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FvbGetAttributes(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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OUT EFI_FVB_ATTRIBUTES_2 *Attributes
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);
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EFI_STATUS
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EFIAPI
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FvbSetAttributes(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
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);
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EFI_STATUS
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EFIAPI
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FvbGetPhysicalAddress(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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OUT EFI_PHYSICAL_ADDRESS *Address
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);
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EFI_STATUS
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EFIAPI
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FvbGetBlockSize(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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IN EFI_LBA Lba,
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OUT UINTN *BlockSize,
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OUT UINTN *NumberOfBlocks
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);
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EFI_STATUS
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EFIAPI
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FvbRead(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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IN EFI_LBA Lba,
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IN UINTN Offset,
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IN OUT UINTN *NumBytes,
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IN OUT UINT8 *Buffer
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);
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EFI_STATUS
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EFIAPI
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FvbWrite(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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IN EFI_LBA Lba,
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IN UINTN Offset,
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IN OUT UINTN *NumBytes,
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IN UINT8 *Buffer
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);
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EFI_STATUS
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EFIAPI
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FvbEraseBlocks(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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...
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);
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//
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// NorFlashDxe.c
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//
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EFI_STATUS
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NorFlashUnlockAndEraseSingleBlock (
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IN NOR_FLASH_INSTANCE *Instance,
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IN UINTN BlockAddress
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);
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EFI_STATUS
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NorFlashWriteSingleBlock (
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IN NOR_FLASH_INSTANCE *Instance,
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IN EFI_LBA Lba,
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IN UINTN Offset,
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IN OUT UINTN *NumBytes,
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IN UINT8 *Buffer
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);
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EFI_STATUS
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NorFlashWriteBlocks (
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IN NOR_FLASH_INSTANCE *Instance,
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IN EFI_LBA Lba,
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IN UINTN BufferSizeInBytes,
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IN VOID *Buffer
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);
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EFI_STATUS
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NorFlashReadBlocks (
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IN NOR_FLASH_INSTANCE *Instance,
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IN EFI_LBA Lba,
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IN UINTN BufferSizeInBytes,
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OUT VOID *Buffer
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);
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EFI_STATUS
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NorFlashRead (
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IN NOR_FLASH_INSTANCE *Instance,
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IN EFI_LBA Lba,
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IN UINTN Offset,
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IN UINTN BufferSizeInBytes,
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OUT VOID *Buffer
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);
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EFI_STATUS
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NorFlashWrite (
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IN NOR_FLASH_INSTANCE *Instance,
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IN EFI_LBA Lba,
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IN UINTN Offset,
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IN OUT UINTN *NumBytes,
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IN UINT8 *Buffer
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);
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EFI_STATUS
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NorFlashReset (
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IN NOR_FLASH_INSTANCE *Instance
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);
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EFI_STATUS
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NorFlashReadID (
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IN NOR_FLASH_INSTANCE *Instance,
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OUT UINT8 JedecId[3]
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);
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#define SPINOR_SR_WIP BIT0 // Write in progress
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#define SPINOR_FSR_READY BIT7 // Flag Status Register: ready
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#define SPINOR_OP_WREN 0x06 // Write enable
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#define SPINOR_OP_WRDIS 0x04 // Write enable
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#define SPINOR_OP_RDSR 0x05 // Read status register
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#define SPINOR_OP_WRSR 0x01 // Write status register 1 byte
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#define SPINOR_OP_RDSR2 0x3f // Read status register 2
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#define SPINOR_OP_WRSR2 0x3e // Write status register 2
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#define SPINOR_OP_READ 0x03 // Read data bytes (low frequency)
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#define SPINOR_OP_READ_FAST 0x0b // Read data bytes (high frequency)
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#define SPINOR_OP_READ_1_1_2 0x3b // Read data bytes (Dual Output SPI)
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#define SPINOR_OP_READ_1_2_2 0xbb // Read data bytes (Dual I/O SPI)
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#define SPINOR_OP_READ_1_1_4 0x6b // Read data bytes (Quad Output SPI)
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#define SPINOR_OP_READ_1_4_4 0xeb // Read data bytes (Quad I/O SPI)
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#define SPINOR_OP_PP 0x02 // Page program (up to 256 bytes)
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#define SPINOR_OP_PP_1_1_4 0x32 // Quad page program
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#define SPINOR_OP_PP_1_4_4 0x38 // Quad page program
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#define SPINOR_OP_BE_4K 0x20 // Erase 4KiB block
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#define SPINOR_OP_BE_4K_PMC 0xd7 // Erase 4KiB block on PMC chips
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#define SPINOR_OP_BE_32K 0x52 // Erase 32KiB block
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#define SPINOR_OP_CHIP_ERASE 0xc7 // Erase whole flash chip
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#define SPINOR_OP_SE 0xd8 // Sector erase (usually 64KiB)
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#define SPINOR_OP_RDID 0x9f // Read JEDEC ID
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#define SPINOR_OP_RDSFDP 0x5a // Read SFDP
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#define SPINOR_OP_RDCR 0x35 // Read configuration register
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#define SPINOR_OP_RDFSR 0x70 // Read flag status register
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#define SPINOR_OP_READ_4B 0x13 // Read data bytes (low frequency)
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#define SPINOR_OP_READ_FAST_4B 0x0c // Read data bytes (high frequency)
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#define SPINOR_OP_READ_1_1_2_4B 0x3c // Read data bytes (Dual Output SPI)
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#define SPINOR_OP_READ_1_2_2_4B 0xbc // Read data bytes (Dual I/O SPI)
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#define SPINOR_OP_READ_1_1_4_4B 0x6c // Read data bytes (Quad Output SPI)
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#define SPINOR_OP_READ_1_4_4_4B 0xec // Read data bytes (Quad I/O SPI)
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#define SPINOR_OP_PP_4B 0x12 // Page program (up to 256 bytes)
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#define SPINOR_OP_PP_1_1_4_4B 0x34 // Quad page program
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#define SPINOR_OP_PP_1_4_4_4B 0x3e // Quad page program
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#define SPINOR_OP_BE_4K_4B 0x21 // Erase 4KiB block
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#define SPINOR_OP_BE_32K_4B 0x5c // Erase 32KiB block
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#define SPINOR_OP_SE_4B 0xdc // Sector erase (usually 64KiB)
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#define SPINOR_OP_RD_ARRAY 0xe8 // Read array
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#define SPINOR_OP_RD_NVCFG 0xb5 // Read non-volatile config register
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#define SPINOR_OP_RD_VCR 0x85 // Read VCR register
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#define SPINOR_OP_RD_EVCR 0x65 // Read EVCR register
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#endif /* __NOR_FLASH_DXE_H__ */
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