/** @file
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Header file for CpuPcieRpLib.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_PCIERP_LIB_H_
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#define _CPU_PCIERP_LIB_H_
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#include <Ppi/SiPolicy.h>
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#include <Library/HobLib.h>
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#pragma pack(1)
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typedef struct {
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UINT8 Segment;
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UINT8 Bus;
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UINT8 Device;
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UINT8 Function;
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BOOLEAN Enable;
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} CPU_PCIE_RP_INFO;
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#pragma pack()
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/**
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Determines whether PCIe link is active
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@param[in] RpBase Root Port base address
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@retval Link Active state
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**/
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BOOLEAN
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CpuPcieIsLinkActive (
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UINT64 RpBase
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);
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/**
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Get max PCIe link speed supported by the root port.
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@param[in] RpBase Root Port pci segment base address
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@return Max link speed
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**/
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UINT32
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CpuPcieGetMaxLinkSpeed (
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UINT64 RpBase
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);
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#endif // _CPU_PCIERP_LIB_H_
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