/** @file
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Library functions for Setting QNC internal network port
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __QNC_ACCESS_LIB_H__
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#define __QNC_ACCESS_LIB_H__
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#include <IntelQNCRegs.h>
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#define MESSAGE_READ_DW(Port, Reg) \
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(UINT32)((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define MESSAGE_WRITE_DW(Port, Reg) \
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(UINT32)((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define ALT_MESSAGE_READ_DW(Port, Reg) \
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(UINT32)((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define ALT_MESSAGE_WRITE_DW(Port, Reg) \
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(UINT32)((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define MESSAGE_IO_READ_DW(Port, Reg) \
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(UINT32)((QUARK_OPCODE_IO_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define MESSAGE_IO_WRITE_DW(Port, Reg) \
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(UINT32)((QUARK_OPCODE_IO_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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#define MESSAGE_SHADOW_DW(Port, Reg) \
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(UINT32)((QUARK_DRAM_BASE_ADDR_READY << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
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/**
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Read required data from QNC internal message network
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**/
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UINT32
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EFIAPI
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QNCPortRead(
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UINT8 Port,
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UINT32 RegAddress
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);
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/**
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Write prepared data into QNC internal message network.
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**/
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VOID
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EFIAPI
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QNCPortWrite (
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UINT8 Port,
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UINT32 RegAddress,
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UINT32 WriteValue
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);
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/**
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Read required data from QNC internal message network
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**/
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UINT32
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EFIAPI
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QNCAltPortRead(
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UINT8 Port,
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UINT32 RegAddress
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);
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/**
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Write prepared data into QNC internal message network.
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**/
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VOID
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EFIAPI
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QNCAltPortWrite (
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UINT8 Port,
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UINT32 RegAddress,
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UINT32 WriteValue
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);
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/**
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Read required data from QNC internal message network
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**/
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UINT32
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EFIAPI
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QNCPortIORead(
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UINT8 Port,
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UINT32 RegAddress
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);
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/**
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Write prepared data into QNC internal message network.
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**/
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VOID
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EFIAPI
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QNCPortIOWrite (
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UINT8 Port,
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UINT32 RegAddress,
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UINT32 WriteValue
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);
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/**
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This is for the special consideration for QNC MMIO write, as required by FWG,
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a reading must be performed after MMIO writing to ensure the expected write
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is processed and data is flushed into chipset
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**/
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RETURN_STATUS
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EFIAPI
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QNCMmIoWrite (
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UINT32 MmIoAddress,
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QNC_MEM_IO_WIDTH Width,
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UINT32 DataNumber,
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VOID *pData
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);
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UINT32
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EFIAPI
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QncHsmmcRead (
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VOID
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);
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VOID
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EFIAPI
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QncHsmmcWrite (
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UINT32 WriteValue
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);
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VOID
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EFIAPI
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QncImrWrite (
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UINT32 ImrBaseOffset,
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UINT32 ImrLow,
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UINT32 ImrHigh,
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UINT32 ImrReadMask,
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UINT32 ImrWriteMask
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);
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VOID
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EFIAPI
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QncIClkAndThenOr (
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UINT32 RegAddress,
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UINT32 AndValue,
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UINT32 OrValue
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);
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VOID
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EFIAPI
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QncIClkOr (
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UINT32 RegAddress,
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UINT32 OrValue
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);
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UINTN
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EFIAPI
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QncGetPciExpressBaseAddress (
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VOID
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);
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#endif
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