/** @file
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CIO2 policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CIO2_CONFIG_H_
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#define _CIO2_CONFIG_H_
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#define CIO2_CONFIG_REVISION 1
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extern EFI_GUID gCio2ConfigGuid;
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#pragma pack (push,1)
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///
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/// The PCH_SKYCAM_CIO2_CONFIG block describes SkyCam CIO2 device.
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///
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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NOTE: For SKL PCH, while CIO2 is enabled,
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RC will configure CIO2 controller as ACPI mode when PCH stepping < C0, and configure to PCI mode for C0 onwards.
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**/
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UINT32 DeviceEnable : 2; ///< 0: Disabled, <b>1: Enabled</b>
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UINT32 SkyCamPortATermOvrEnable : 1; ///< <b>0: Disable</b>, 1: Enable - Termination override on port A
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UINT32 SkyCamPortBTermOvrEnable : 1; ///< <b>0: Disable</b>, 1: Enable - Termination override on port B
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UINT32 SkyCamPortCTermOvrEnable : 1; ///< <b>0: Disable</b>, 1: Enable - Termination override on port C
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UINT32 SkyCamPortDTermOvrEnable : 1; ///< <b>0: Disable</b>, 1: Enable - Termination override on port D
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UINT32 RsvdBits : 26;
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//
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// CIO2 FLS registers configuration.
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//
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UINT32 PortATrimEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port A Clk Trim
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UINT32 PortBTrimEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port B Clk Trim
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UINT32 PortCTrimEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port C Clk Trim
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UINT32 PortDTrimEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port D Clk Trim
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UINT32 PortACtleEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port A Ctle
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UINT32 PortBCtleEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port B Ctle
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UINT32 PortCDCtleEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port C/D Ctle
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UINT32 RsvdBits0 : 25;
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UINT32 PortACtleCapValue : 4; /// Port A Ctle Cap Value. Default is <b>0xE</b>
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UINT32 PortBCtleCapValue : 4; /// Port B Ctle Cap Value. Default is <b>0xE</b>
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UINT32 PortCDCtleCapValue : 4; /// Port C/D Ctle Cap Value. Default is <b>0xE</b>
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UINT32 PortACtleResValue : 5; /// Port A Ctle Res Value. Default is <b>0xD</b>
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UINT32 PortBCtleResValue : 5; /// Port B Ctle Res Value. Default is <b>0xD</b>
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UINT32 PortCDCtleResValue : 5; /// Port C/D Ctle Res Value. Default is <b>0xD</b>
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UINT32 RsvdBits1 : 5;
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UINT32 PortAClkTrimValue : 4; /// Port A Clk Trim Value. Default is <b>0xA</b>
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UINT32 PortBClkTrimValue : 4; /// Port B Clk Trim Value. Default is <b>0xA</b>
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UINT32 PortCClkTrimValue : 4; /// Port C Clk Trim Value. Default is <b>0x9</b>
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UINT32 PortDClkTrimValue : 4; /// Port D Clk Trim Value. Default is <b>0xA</b>
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UINT32 PortADataTrimValue : 16; /// Port A Data Trim Value. Default is <b>0xBBBB</b>
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UINT32 PortBDataTrimValue : 16; /// Port B Data Trim Value. Default is <b>0xBBBB</b>
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UINT32 PortCDDataTrimValue : 16; /// Port C/D Data Trim Value. Default is <b>0xCCCC</b>
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} PCH_CIO2_CONFIG;
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#pragma pack (pop)
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#endif // _CIO2_CONFIG_H_
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