/** @file
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Register names for PCH P2SB device
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used .
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -H denoted by "_PCH_H_" in component name.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_P2SB_H_
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#define _PCH_REGS_P2SB_H_
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//
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// PCI to P2SB Bridge Registers (D31:F1)
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//
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#define PCI_DEVICE_NUMBER_PCH_P2SB 31
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#define PCI_FUNCTION_NUMBER_PCH_P2SB 1
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#define V_P2SB_CFG_VENDOR_ID V_PCH_INTEL_VENDOR_ID
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#define R_P2SB_CFG_SBREG_BAR 0x10
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#define B_P2SB_CFG_SBREG_RBA 0xFF000000
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#define R_P2SB_CFG_SBREG_BARH 0x14
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#define B_P2SB_CFG_SBREG_RBAH 0xFFFFFFFF
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#define R_P2SB_CFG_VBDF 0x50
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#define B_P2SB_CFG_VBDF_BUS 0xFF00
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#define B_P2SB_CFG_VBDF_DEV 0x00F8
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#define B_P2SB_CFG_VBDF_FUNC 0x0007
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#define R_P2SB_CFG_ESMBDF 0x52
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#define B_P2SB_CFG_ESMBDF_BUS 0xFF00
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#define B_P2SB_CFG_ESMBDF_DEV 0x00F8
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#define B_P2SB_CFG_ESMBDF_FUNC 0x0007
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#define R_P2SB_CFG_RCFG 0x54
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#define B_P2SB_CFG_RCFG_RPRID 0x0000FF00
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#define B_P2SB_CFG_RCFG_RSE BIT0
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#define R_P2SB_CFG_HPTC 0x60
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#define B_P2SB_CFG_HPTC_AE BIT7
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#define B_P2SB_CFG_HPTC_AS 0x0003
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#define N_HPET_ADDR_ASEL 12
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#define R_P2SB_CFG_IOAC 0x64
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#define B_P2SB_CFG_IOAC_AE BIT8
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#define B_P2SB_CFG_IOAC_ASEL 0x00FF
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#define N_IO_APIC_ASEL 12
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#define R_IO_APIC_INDEX_OFFSET 0x00
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#define R_IO_APIC_DATA_OFFSET 0x10
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#define R_IO_APIC_EOI_OFFSET 0x40
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#define R_P2SB_CFG_IBDF 0x6C
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#define B_P2SB_CFG_IBDF_BUS 0xFF00
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#define B_P2SB_CFG_IBDF_DEV 0x00F8
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#define B_P2SB_CFG_IBDF_FUNC 0x0007
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#define V_P2SB_CFG_IBDF_BUS 0
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#define V_P2SB_CFG_IBDF_DEV 30
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#define V_P2SB_CFG_IBDF_FUNC 7
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#define V_P2SB_CFG_HBDF_BUS 0
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#define V_P2SB_CFG_HBDF_DEV 30
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#define V_P2SB_CFG_HBDF_FUNC 6
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//
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// Definition for SBI
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//
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#define R_P2SB_CFG_SBIADDR 0xD0
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#define B_P2SB_CFG_SBIADDR_DESTID 0xFF000000
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#define B_P2SB_CFG_SBIADDR_RS 0x000F0000
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#define B_P2SB_CFG_SBIADDR_OFFSET 0x0000FFFF
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#define R_P2SB_CFG_SBIDATA 0xD4
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#define B_P2SB_CFG_SBIDATA_DATA 0xFFFFFFFF
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#define R_P2SB_CFG_SBISTAT 0xD8
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#define B_P2SB_CFG_SBISTAT_OPCODE 0xFF00
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#define B_P2SB_CFG_SBISTAT_POSTED BIT7
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#define B_P2SB_CFG_SBISTAT_RESPONSE 0x0006
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#define N_P2SB_CFG_SBISTAT_RESPONSE 1
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#define B_P2SB_CFG_SBISTAT_INITRDY BIT0
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#define R_P2SB_CFG_SBIRID 0xDA
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#define B_P2SB_CFG_SBIRID_FBE 0xF000
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#define B_P2SB_CFG_SBIRID_BAR 0x0700
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#define B_P2SB_CFG_SBIRID_FID 0x00FF
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#define R_P2SB_CFG_SBIEXTADDR 0xDC
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#define B_P2SB_CFG_SBIEXTADDR_ADDR 0xFFFFFFFF
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//
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// Others
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//
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#define R_P2SB_CFG_E0 0xE0
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#define R_P2SB_CFG_E4 0xE4
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#define R_P2SB_CFG_E8 0xE8
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#define R_P2SB_CFG_EA 0xEA
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#define R_P2SB_CFG_F4 0xF4
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#endif
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