/** @file
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Header file with all common HSIO information
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_HSIO_H_
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#define _PCH_HSIO_H_
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#define PCH_LANE_OWN_COMMON 0x10
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#define PCH_LANE_BDCAST 0x11
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#define PCH_HSIO_LANE_GROUP_NO 0x09
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#define PCH_HSIO_LANE_GROUP_COMMON_LANE 0x00
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#define PCH_HSIO_LANE_GROUP_PCIE 0x01
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#define PCH_HSIO_LANE_GROUP_DMI 0x02
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#define PCH_HSIO_LANE_GROUP_GBE 0x03
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#define PCH_HSIO_LANE_GROUP_USB3 0x04
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#define PCH_HSIO_LANE_GROUP_SATA 0x05
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#define PCH_HSIO_LANE_GROUP_SSIC 0x06
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/**
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PCH HSIO ChipsetInit Version Information
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**/
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typedef struct {
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UINT16 BaseCrc;
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UINT16 SusCrc;
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UINT16 OemCrc;
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UINT8 Version;
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UINT8 Product;
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UINT8 MetalLayer : 4;
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UINT8 BaseLayer : 4;
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UINT8 OemVersion;
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UINT16 DebugMode : 1;
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UINT16 OemCrcValid : 1;
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UINT16 SusCrcValid : 1;
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UINT16 BaseCrcValid : 1;
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UINT16 Reserved : 12;
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} PCH_HSIO_VER_INFO;
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#define PMC_DATA_CMD_SIZE ((12/sizeof(UINT16))-1)
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#define PMC_DATA_DELAY_CMD_SIZE ((4/sizeof(UINT16))-1)
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#define RECORD_OFFSET(X, Y) ((X << 4) | Y)
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/**
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PCH HSIO ChipsetInit Command Field
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**/
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typedef struct {
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UINT8 Command : 3;
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UINT8 Size : 5;
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UINT8 Pid;
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UINT8 OpCode; //PrivateControlWrite
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UINT8 Bar; //0
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UINT8 Fbe; //First Byte Enable : 0x0F
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UINT8 Fid; //0
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UINT16 Offset;
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UINT32 Value;
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} PCH_HSIO_CMD_FIELD;
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/**
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PCH HSIO Delay XRAM Data
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**/
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typedef struct {
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UINT8 Command : 3;
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UINT8 Size : 5;
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UINT8 DelayPeriod; //(00h = 1us, 01h = 10us, 02h = 100us, ..., 07h = 10s; others reserved)
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UINT8 DelayCount; //(0 - 255); total delay = Delay period * Delay count
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UINT8 Padding;
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} PCH_HSIO_DELAY_CMD_FIELD;
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typedef enum {
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Delay1us = 0x0,
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Delay10us,
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Delay100us,
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Delay1ms,
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Delay10ms,
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Delay100ms,
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Delay1s,
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Delay10s
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} PCH_HSIO_DELAY;
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/**
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PCH PCIE PLL SSC Data
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**/
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#define MAX_PCIE_PLL_SSC_PERCENT 20
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#include <Private/CnlPchLpHsioDx.h>
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#endif //_PCH_HSIO_H_
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