/*
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* definitions for MPC8xxx I/O Ports
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*
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* Murray.Jensen@cmst.csiro.au, 20-Oct-00
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*/
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/*
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* this structure mirrors the layout of the five port registers in
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* the internal memory map
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*/
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typedef struct {
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unsigned int pdir; /* Port Data Direction Register (35-3) */
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unsigned int ppar; /* Port Pin Assignment Register (35-4) */
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unsigned int psor; /* Port Special Options Register (35-5) */
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unsigned int podr; /* Port Open Drain Register (35-2) */
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unsigned int pdat; /* Port Data Register (35-3) */
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} ioport_t;
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/*
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* this macro calculates the address within the internal
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* memory map (im) of the set of registers for a port (idx)
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*
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* the internal memory map aligns the above structure on
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* a 0x20 byte boundary
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*/
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#ifdef CONFIG_MPC85xx
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#define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20))
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#else
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#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
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#endif
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/*
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* this structure provides configuration
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* information for one port pin
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*/
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typedef struct {
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unsigned char conf:1; /* if 1, configure this port */
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unsigned char ppar:1; /* Port Pin Assignment Register (35-4) */
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unsigned char psor:1; /* Port Special Options Register (35-2) */
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unsigned char pdir:1; /* Port Data Direction Register (35-3) */
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unsigned char podr:1; /* Port Open Drain Register (35-2) */
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unsigned char pdat:1; /* Port Data Register (35-2) */
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} iop_conf_t;
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/*
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* a table that contains configuration information for all 32 pins
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*
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* NOTE: in the second dimension of this table, index 0 refers to pin 31
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* and index 31 refers to pin 0. this made the code in the table look more
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* like the table in the 8260UM (and in the hymod manuals).
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*/
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extern const iop_conf_t iop_conf_tab[4][32];
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typedef struct {
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unsigned char port;
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unsigned char pin;
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int dir;
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int open_drain;
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int assign;
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} qe_iop_conf_t;
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#define QE_IOP_TAB_END (-1)
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