/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 Cadence Design Systems Inc.
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*/
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#ifndef __PHY_DP_H_
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#define __PHY_DP_H_
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/**
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* struct phy_configure_opts_dp - DisplayPort PHY configuration set
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*
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* This structure is used to represent the configuration state of a
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* DisplayPort phy.
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*/
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struct phy_configure_opts_dp {
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/**
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* @link_rate:
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*
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* Link Rate, in Mb/s, of the main link.
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*
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* Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
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*/
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unsigned int link_rate;
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/**
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* @lanes:
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*
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* Number of active, consecutive, data lanes, starting from
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* lane 0, used for the transmissions on main link.
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*
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* Allowed values: 1, 2, 4
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*/
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unsigned int lanes;
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/**
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* @voltage:
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*
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* Voltage swing levels, as specified by DisplayPort specification,
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* to be used by particular lanes. One value per lane.
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* voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
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*
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* Maximum value: 3
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*/
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unsigned int voltage[4];
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/**
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* @pre:
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*
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* Pre-emphasis levels, as specified by DisplayPort specification, to be
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* used by particular lanes. One value per lane.
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*
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* Maximum value: 3
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*/
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unsigned int pre[4];
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/**
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* @ssc:
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*
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* Flag indicating, whether or not to enable spread-spectrum clocking.
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*
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*/
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u8 ssc : 1;
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/**
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* @set_rate:
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*
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* Flag indicating, whether or not reconfigure link rate and SSC to
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* requested values.
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*
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*/
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u8 set_rate : 1;
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/**
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* @set_lanes:
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*
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* Flag indicating, whether or not reconfigure lane count to
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* requested value.
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*
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*/
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u8 set_lanes : 1;
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/**
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* @set_voltages:
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*
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* Flag indicating, whether or not reconfigure voltage swing
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* and pre-emphasis to requested values. Only lanes specified
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* by "lanes" parameter will be affected.
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*
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*/
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u8 set_voltages : 1;
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};
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#endif /* __PHY_DP_H_ */
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