/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <linux/err.h>
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int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct sysreset_reg *offset = dev_get_priv(dev);
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unsigned long cru_base = (unsigned long)dev_read_addr_ptr(dev->parent);
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if (IS_ERR_VALUE(cru_base))
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return (int)cru_base;
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switch (type) {
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case SYSRESET_WARM:
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#ifdef CONFIG_ARM64
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/* Rockchip 64bit SOC need fst reset for cpu reset entry */
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writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
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#else
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writel(0xeca8, cru_base + offset->glb_srst_snd_value);
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#endif
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break;
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case SYSRESET_COLD:
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writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops rockchip_sysreset = {
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.request = rockchip_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_rockchip) = {
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.name = "rockchip_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &rockchip_sysreset,
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};
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