/*
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* Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on source code of Shlomi Gridish
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __UEC_H__
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#define __UEC_H__
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#include "uccf.h"
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#include <fsl_qe.h>
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#include <phy.h>
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#define MAX_TX_THREADS 8
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#define MAX_RX_THREADS 8
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#define MAX_TX_QUEUES 8
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#define MAX_RX_QUEUES 8
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#define MAX_PREFETCHED_BDS 4
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#define MAX_IPH_OFFSET_ENTRY 8
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#define MAX_ENET_INIT_PARAM_ENTRIES_RX 9
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#define MAX_ENET_INIT_PARAM_ENTRIES_TX 8
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/* UEC UPSMR (Protocol Specific Mode Register)
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*/
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#define UPSMR_ECM 0x04000000 /* Enable CAM Miss */
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#define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */
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#define UPSMR_PRO 0x00400000 /* Promiscuous */
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#define UPSMR_CAP 0x00200000 /* CAM polarity */
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#define UPSMR_RSH 0x00100000 /* Receive Short Frames */
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#define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */
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#define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */
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#define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */
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#define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
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#define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */
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#define UPSMR_CAM 0x00000400 /* CAM Address Matching */
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#define UPSMR_BRO 0x00000200 /* Broadcast Address */
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#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
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#define UPSMR_SGMM 0x00000020 /* SGMII mode */
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#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
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/* UEC MACCFG1 (MAC Configuration 1 Register)
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*/
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#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */
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#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */
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#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */
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#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
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#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */
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#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
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#define MACCFG1_INIT_VALUE (0)
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/* UEC MACCFG2 (MAC Configuration 2 Register)
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*/
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#define MACCFG2_PREL 0x00007000
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#define MACCFG2_PREL_SHIFT (31 - 19)
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#define MACCFG2_PREL_MASK 0x0000f000
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#define MACCFG2_SRP 0x00000080
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#define MACCFG2_STP 0x00000040
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#define MACCFG2_RESERVED_1 0x00000020 /* must be set */
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#define MACCFG2_LC 0x00000010 /* Length Check */
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#define MACCFG2_MPE 0x00000008
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#define MACCFG2_FDX 0x00000001 /* Full Duplex */
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#define MACCFG2_FDX_MASK 0x00000001
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#define MACCFG2_PAD_CRC 0x00000004
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#define MACCFG2_CRC_EN 0x00000002
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#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000
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#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002
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#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
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#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100
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#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200
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#define MACCFG2_INTERFACE_MODE_MASK 0x00000300
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#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
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MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
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/* UEC Event Register
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*/
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#define UCCE_MPD 0x80000000
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#define UCCE_SCAR 0x40000000
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#define UCCE_GRA 0x20000000
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#define UCCE_CBPR 0x10000000
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#define UCCE_BSY 0x08000000
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#define UCCE_RXC 0x04000000
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#define UCCE_TXC 0x02000000
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#define UCCE_TXE 0x01000000
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#define UCCE_TXB7 0x00800000
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#define UCCE_TXB6 0x00400000
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#define UCCE_TXB5 0x00200000
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#define UCCE_TXB4 0x00100000
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#define UCCE_TXB3 0x00080000
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#define UCCE_TXB2 0x00040000
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#define UCCE_TXB1 0x00020000
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#define UCCE_TXB0 0x00010000
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#define UCCE_RXB7 0x00008000
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#define UCCE_RXB6 0x00004000
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#define UCCE_RXB5 0x00002000
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#define UCCE_RXB4 0x00001000
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#define UCCE_RXB3 0x00000800
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#define UCCE_RXB2 0x00000400
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#define UCCE_RXB1 0x00000200
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#define UCCE_RXB0 0x00000100
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#define UCCE_RXF7 0x00000080
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#define UCCE_RXF6 0x00000040
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#define UCCE_RXF5 0x00000020
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#define UCCE_RXF4 0x00000010
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#define UCCE_RXF3 0x00000008
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#define UCCE_RXF2 0x00000004
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#define UCCE_RXF1 0x00000002
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#define UCCE_RXF0 0x00000001
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#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
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UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
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#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
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UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
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#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
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UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
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#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \
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UCCE_RXC | UCCE_TXC | UCCE_TXE)
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/* UEC TEMODR Register
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*/
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#define TEMODER_SCHEDULER_ENABLE 0x2000
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#define TEMODER_IP_CHECKSUM_GENERATE 0x0400
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#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
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#define TEMODER_RMON_STATISTICS 0x0100
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#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15)
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#define TEMODER_INIT_VALUE 0xc000
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/* UEC REMODR Register
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*/
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#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
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#define REMODER_RX_EXTENDED_FEATURES 0x80000000
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#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 )
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#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
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#define REMODER_RX_QOS_MODE_SHIFT (31-15)
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#define REMODER_RMON_STATISTICS 0x00001000
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#define REMODER_RX_EXTENDED_FILTERING 0x00000800
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#define REMODER_NUM_OF_QUEUES_SHIFT (31-23)
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#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
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#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
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#define REMODER_IP_CHECKSUM_CHECK 0x00000002
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#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001
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#define REMODER_INIT_VALUE 0
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/* BMRx - Bus Mode Register */
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#define BMR_GLB 0x20
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#define BMR_BO_BE 0x10
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#define BMR_DTB_SECONDARY_BUS 0x02
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#define BMR_BDB_SECONDARY_BUS 0x01
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#define BMR_SHIFT 24
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#define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE)
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/* UEC UCCS (Ethernet Status Register)
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*/
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#define UCCS_BPR 0x02
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#define UCCS_PAU 0x02
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#define UCCS_MPD 0x01
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/* UEC MIIMCFG (MII Management Configuration Register)
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*/
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#define MIIMCFG_RESET_MANAGEMENT 0x80000000
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#define MIIMCFG_NO_PREAMBLE 0x00000010
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#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31)
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#define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006
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#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007
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#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \
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MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
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/* UEC MIIMCOM (MII Management Command Register)
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*/
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#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
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#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
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/* UEC MIIMADD (MII Management Address Register)
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*/
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#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23)
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#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31)
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/* UEC MIIMCON (MII Management Control Register)
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*/
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#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31)
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#define MIIMCON_PHY_STATUS_SHIFT (31 - 31)
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/* UEC MIIMIND (MII Management Indicator Register)
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*/
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#define MIIMIND_NOT_VALID 0x00000004
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#define MIIMIND_SCAN 0x00000002
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#define MIIMIND_BUSY 0x00000001
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/* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
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*/
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#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
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#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f
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/* UEC UESCR (Ethernet Statistics Control Register)
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*/
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#define UESCR_AUTOZ 0x8000
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#define UESCR_CLRCNT 0x4000
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#define UESCR_MAXCOV_SHIFT (15 - 7)
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#define UESCR_SCOV_SHIFT (15 - 15)
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/****** Tx data struct collection ******/
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/* Tx thread data, each Tx thread has one this struct.
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*/
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typedef struct uec_thread_data_tx {
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u8 res0[136];
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} __attribute__ ((packed)) uec_thread_data_tx_t;
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/* Tx thread parameter, each Tx thread has one this struct.
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*/
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typedef struct uec_thread_tx_pram {
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u8 res0[64];
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} __attribute__ ((packed)) uec_thread_tx_pram_t;
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/* Send queue queue-descriptor, each Tx queue has one this QD
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*/
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typedef struct uec_send_queue_qd {
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u32 bd_ring_base; /* pointer to BD ring base address */
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u8 res0[0x8];
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u32 last_bd_completed_address; /* last entry in BD ring */
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u8 res1[0x30];
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} __attribute__ ((packed)) uec_send_queue_qd_t;
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/* Send queue memory region */
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typedef struct uec_send_queue_mem_region {
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uec_send_queue_qd_t sqqd[MAX_TX_QUEUES];
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} __attribute__ ((packed)) uec_send_queue_mem_region_t;
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/* Scheduler struct
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*/
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typedef struct uec_scheduler {
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u16 cpucount0; /* CPU packet counter */
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u16 cpucount1; /* CPU packet counter */
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u16 cecount0; /* QE packet counter */
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u16 cecount1; /* QE packet counter */
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u16 cpucount2; /* CPU packet counter */
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u16 cpucount3; /* CPU packet counter */
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u16 cecount2; /* QE packet counter */
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u16 cecount3; /* QE packet counter */
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u16 cpucount4; /* CPU packet counter */
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u16 cpucount5; /* CPU packet counter */
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u16 cecount4; /* QE packet counter */
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u16 cecount5; /* QE packet counter */
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u16 cpucount6; /* CPU packet counter */
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u16 cpucount7; /* CPU packet counter */
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u16 cecount6; /* QE packet counter */
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u16 cecount7; /* QE packet counter */
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u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
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u32 rtsrshadow; /* temporary variable handled by QE */
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u32 time; /* temporary variable handled by QE */
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u32 ttl; /* temporary variable handled by QE */
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u32 mblinterval; /* max burst length interval */
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u16 nortsrbytetime; /* normalized value of byte time in tsr units */
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u8 fracsiz;
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u8 res0[1];
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u8 strictpriorityq; /* Strict Priority Mask register */
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u8 txasap; /* Transmit ASAP register */
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u8 extrabw; /* Extra BandWidth register */
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u8 oldwfqmask; /* temporary variable handled by QE */
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u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
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u32 minw; /* temporary variable handled by QE */
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u8 res1[0x70-0x64];
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} __attribute__ ((packed)) uec_scheduler_t;
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/* Tx firmware counters
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*/
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typedef struct uec_tx_firmware_statistics_pram {
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u32 sicoltx; /* single collision */
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u32 mulcoltx; /* multiple collision */
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u32 latecoltxfr; /* late collision */
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u32 frabortduecol; /* frames aborted due to tx collision */
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u32 frlostinmactxer; /* frames lost due to internal MAC error tx */
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u32 carriersenseertx; /* carrier sense error */
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u32 frtxok; /* frames transmitted OK */
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u32 txfrexcessivedefer;
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u32 txpkts256; /* total packets(including bad) 256~511 B */
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u32 txpkts512; /* total packets(including bad) 512~1023B */
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u32 txpkts1024; /* total packets(including bad) 1024~1518B */
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u32 txpktsjumbo; /* total packets(including bad) >1024 */
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} __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t;
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/* Tx global parameter table
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*/
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typedef struct uec_tx_global_pram {
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u16 temoder;
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u8 res0[0x38-0x02];
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u32 sqptr;
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u32 schedulerbasepointer;
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u32 txrmonbaseptr;
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u32 tstate;
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u8 iphoffset[MAX_IPH_OFFSET_ENTRY];
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u32 vtagtable[0x8];
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u32 tqptr;
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u8 res2[0x80-0x74];
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} __attribute__ ((packed)) uec_tx_global_pram_t;
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/****** Rx data struct collection ******/
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/* Rx thread data, each Rx thread has one this struct.
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*/
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typedef struct uec_thread_data_rx {
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u8 res0[40];
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} __attribute__ ((packed)) uec_thread_data_rx_t;
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/* Rx thread parameter, each Rx thread has one this struct.
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*/
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typedef struct uec_thread_rx_pram {
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u8 res0[128];
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} __attribute__ ((packed)) uec_thread_rx_pram_t;
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/* Rx firmware counters
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*/
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typedef struct uec_rx_firmware_statistics_pram {
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u32 frrxfcser; /* frames with crc error */
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u32 fraligner; /* frames with alignment error */
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u32 inrangelenrxer; /* in range length error */
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u32 outrangelenrxer; /* out of range length error */
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u32 frtoolong; /* frame too long */
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u32 runt; /* runt */
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u32 verylongevent; /* very long event */
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u32 symbolerror; /* symbol error */
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u32 dropbsy; /* drop because of BD not ready */
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u8 res0[0x8];
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u32 mismatchdrop; /* drop because of MAC filtering */
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u32 underpkts; /* total frames less than 64 octets */
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u32 pkts256; /* total frames(including bad)256~511 B */
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u32 pkts512; /* total frames(including bad)512~1023 B */
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u32 pkts1024; /* total frames(including bad)1024~1518 B */
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u32 pktsjumbo; /* total frames(including bad) >1024 B */
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u32 frlossinmacer;
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u32 pausefr; /* pause frames */
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u8 res1[0x4];
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u32 removevlan;
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u32 replacevlan;
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u32 insertvlan;
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} __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t;
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/* Rx interrupt coalescing entry, each Rx queue has one this entry.
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*/
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typedef struct uec_rx_interrupt_coalescing_entry {
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u32 maxvalue;
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u32 counter;
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} __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;
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typedef struct uec_rx_interrupt_coalescing_table {
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uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES];
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} __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;
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/* RxBD queue entry, each Rx queue has one this entry.
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*/
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typedef struct uec_rx_bd_queues_entry {
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u32 bdbaseptr; /* BD base pointer */
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u32 bdptr; /* BD pointer */
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u32 externalbdbaseptr; /* external BD base pointer */
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u32 externalbdptr; /* external BD pointer */
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} __attribute__ ((packed)) uec_rx_bd_queues_entry_t;
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/* Rx global paramter table
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*/
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typedef struct uec_rx_global_pram {
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u32 remoder; /* ethernet mode reg. */
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u32 rqptr; /* base pointer to the Rx Queues */
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u32 res0[0x1];
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u8 res1[0x20-0xC];
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u16 typeorlen;
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u8 res2[0x1];
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u8 rxgstpack; /* ack on GRACEFUL STOP RX command */
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u32 rxrmonbaseptr; /* Rx RMON statistics base */
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u8 res3[0x30-0x28];
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u32 intcoalescingptr; /* Interrupt coalescing table pointer */
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u8 res4[0x36-0x34];
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u8 rstate;
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u8 res5[0x46-0x37];
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u16 mrblr; /* max receive buffer length reg. */
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u32 rbdqptr; /* RxBD parameter table description */
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u16 mflr; /* max frame length reg. */
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u16 minflr; /* min frame length reg. */
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u16 maxd1; /* max dma1 length reg. */
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u16 maxd2; /* max dma2 length reg. */
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u32 ecamptr; /* external CAM address */
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u32 l2qt; /* VLAN priority mapping table. */
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u32 l3qt[0x8]; /* IP priority mapping table. */
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u16 vlantype; /* vlan type */
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u16 vlantci; /* default vlan tci */
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u8 addressfiltering[64];/* address filtering data structure */
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u32 exfGlobalParam; /* extended filtering global parameters */
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u8 res6[0x100-0xC4]; /* Initialize to zero */
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} __attribute__ ((packed)) uec_rx_global_pram_t;
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#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
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/****** UEC common ******/
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/* UCC statistics - hardware counters
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*/
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typedef struct uec_hardware_statistics {
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u32 tx64;
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u32 tx127;
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u32 tx255;
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u32 rx64;
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u32 rx127;
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u32 rx255;
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u32 txok;
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u16 txcf;
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u32 tmca;
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u32 tbca;
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u32 rxfok;
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u32 rxbok;
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u32 rbyt;
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u32 rmca;
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u32 rbca;
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} __attribute__ ((packed)) uec_hardware_statistics_t;
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/* InitEnet command parameter
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*/
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typedef struct uec_init_cmd_pram {
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u8 resinit0;
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u8 resinit1;
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u8 resinit2;
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u8 resinit3;
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u16 resinit4;
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u8 res1[0x1];
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u8 largestexternallookupkeysize;
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u32 rgftgfrxglobal;
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u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
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u8 res2[0x38 - 0x30];
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u32 txglobal; /* tx global */
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u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
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u8 res3[0x1];
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} __attribute__ ((packed)) uec_init_cmd_pram_t;
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#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
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#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
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#define ENET_INIT_PARAM_RISC_MASK 0x0000003f
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#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
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#define ENET_INIT_PARAM_SNUM_MASK 0xff000000
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#define ENET_INIT_PARAM_SNUM_SHIFT 24
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#define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06
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#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30
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#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff
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#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00
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#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400
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/* structure representing 82xx Address Filtering Enet Address in PRAM
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*/
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typedef struct uec_82xx_enet_address {
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u8 res1[0x2];
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u16 h; /* address (MSB) */
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u16 m; /* address */
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u16 l; /* address (LSB) */
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} __attribute__ ((packed)) uec_82xx_enet_address_t;
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/* structure representing 82xx Address Filtering PRAM
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*/
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typedef struct uec_82xx_address_filtering_pram {
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u32 iaddr_h; /* individual address filter, high */
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u32 iaddr_l; /* individual address filter, low */
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u32 gaddr_h; /* group address filter, high */
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u32 gaddr_l; /* group address filter, low */
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uec_82xx_enet_address_t taddr;
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uec_82xx_enet_address_t paddr[4];
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u8 res0[0x40-0x38];
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} __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;
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/* Buffer Descriptor
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*/
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typedef struct buffer_descriptor {
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u16 status;
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u16 len;
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u32 data;
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} __attribute__ ((packed)) qe_bd_t, *p_bd_t;
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#define SIZEOFBD sizeof(qe_bd_t)
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/* Common BD flags
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*/
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#define BD_WRAP 0x2000
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#define BD_INT 0x1000
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#define BD_LAST 0x0800
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#define BD_CLEAN 0x3000
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/* TxBD status flags
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*/
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#define TxBD_READY 0x8000
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#define TxBD_PADCRC 0x4000
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#define TxBD_WRAP BD_WRAP
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#define TxBD_INT BD_INT
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#define TxBD_LAST BD_LAST
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#define TxBD_TXCRC 0x0400
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#define TxBD_DEF 0x0200
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#define TxBD_PP 0x0100
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#define TxBD_LC 0x0080
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#define TxBD_RL 0x0040
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#define TxBD_RC 0x003C
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#define TxBD_UNDERRUN 0x0002
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#define TxBD_TRUNC 0x0001
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#define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC)
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/* RxBD status flags
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*/
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#define RxBD_EMPTY 0x8000
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#define RxBD_OWNER 0x4000
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#define RxBD_WRAP BD_WRAP
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#define RxBD_INT BD_INT
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#define RxBD_LAST BD_LAST
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#define RxBD_FIRST 0x0400
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#define RxBD_CMR 0x0200
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#define RxBD_MISS 0x0100
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#define RxBD_BCAST 0x0080
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#define RxBD_MCAST 0x0040
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#define RxBD_LG 0x0020
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#define RxBD_NO 0x0010
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#define RxBD_SHORT 0x0008
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#define RxBD_CRCERR 0x0004
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#define RxBD_OVERRUN 0x0002
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#define RxBD_IPCH 0x0001
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#define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \
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RxBD_CRCERR | RxBD_OVERRUN)
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/* BD access macros
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*/
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#define BD_STATUS(_bd) (((p_bd_t)(_bd))->status)
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#define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val)
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#define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len)
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#define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val)
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#define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0)
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#define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data)
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#define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data))
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#define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data))
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#define BD_ADVANCE(_bd,_status,_base) \
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(((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
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/* Rx Prefetched BDs
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*/
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typedef struct uec_rx_prefetched_bds {
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qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
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} __attribute__ ((packed)) uec_rx_prefetched_bds_t;
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/* Alignments
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*/
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#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64
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#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64
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#define UEC_THREAD_RX_PRAM_ALIGNMENT 128
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#define UEC_THREAD_TX_PRAM_ALIGNMENT 64
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#define UEC_THREAD_DATA_ALIGNMENT 256
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#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
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#define UEC_SCHEDULER_ALIGNMENT 4
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#define UEC_TX_STATISTICS_ALIGNMENT 4
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#define UEC_RX_STATISTICS_ALIGNMENT 4
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#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4
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#define UEC_RX_BD_QUEUES_ALIGNMENT 8
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#define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128
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#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4
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#define UEC_RX_BD_RING_ALIGNMENT 32
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#define UEC_TX_BD_RING_ALIGNMENT 32
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#define UEC_MRBLR_ALIGNMENT 128
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#define UEC_RX_BD_RING_SIZE_ALIGNMENT 4
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#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
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#define UEC_RX_DATA_BUF_ALIGNMENT 64
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#define UEC_VLAN_PRIORITY_MAX 8
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#define UEC_IP_PRIORITY_MAX 64
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#define UEC_TX_VTAG_TABLE_ENTRY_MAX 8
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#define UEC_RX_BD_RING_SIZE_MIN 8
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#define UEC_TX_BD_RING_SIZE_MIN 2
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/* Ethernet speed
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*/
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typedef enum enet_speed {
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ENET_SPEED_10BT, /* 10 Base T */
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ENET_SPEED_100BT, /* 100 Base T */
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ENET_SPEED_1000BT /* 1000 Base T */
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} enet_speed_e;
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/* Ethernet Address Type.
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*/
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typedef enum enet_addr_type {
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ENET_ADDR_TYPE_INDIVIDUAL,
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ENET_ADDR_TYPE_GROUP,
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ENET_ADDR_TYPE_BROADCAST
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} enet_addr_type_e;
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/* TBI / MII Set Register
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*/
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typedef enum enet_tbi_mii_reg {
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ENET_TBI_MII_CR = 0x00,
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ENET_TBI_MII_SR = 0x01,
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ENET_TBI_MII_ANA = 0x04,
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ENET_TBI_MII_ANLPBPA = 0x05,
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ENET_TBI_MII_ANEX = 0x06,
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ENET_TBI_MII_ANNPT = 0x07,
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ENET_TBI_MII_ANLPANP = 0x08,
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ENET_TBI_MII_EXST = 0x0F,
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ENET_TBI_MII_JD = 0x10,
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ENET_TBI_MII_TBICON = 0x11
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} enet_tbi_mii_reg_e;
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/* TBI MDIO register bit fields*/
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#define TBICON_CLK_SELECT 0x0020
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#define TBIANA_ASYMMETRIC_PAUSE 0x0100
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#define TBIANA_SYMMETRIC_PAUSE 0x0080
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#define TBIANA_HALF_DUPLEX 0x0040
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#define TBIANA_FULL_DUPLEX 0x0020
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#define TBICR_PHY_RESET 0x8000
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#define TBICR_ANEG_ENABLE 0x1000
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#define TBICR_RESTART_ANEG 0x0200
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#define TBICR_FULL_DUPLEX 0x0100
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#define TBICR_SPEED1_SET 0x0040
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|
#define TBIANA_SETTINGS ( \
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TBIANA_ASYMMETRIC_PAUSE \
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| TBIANA_SYMMETRIC_PAUSE \
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| TBIANA_FULL_DUPLEX \
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)
|
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#define TBICR_SETTINGS ( \
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TBICR_PHY_RESET \
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| TBICR_ANEG_ENABLE \
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| TBICR_FULL_DUPLEX \
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| TBICR_SPEED1_SET \
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)
|
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/* UEC number of threads
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*/
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typedef enum uec_num_of_threads {
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UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */
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UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */
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UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */
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UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */
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UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
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} uec_num_of_threads_e;
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|
/* UEC initialization info struct
|
*/
|
#define STD_UEC_INFO(num) \
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{ \
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.uf_info = { \
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.ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
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.rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
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.tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
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.eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
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}, \
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.num_threads_tx = UEC_NUM_OF_THREADS_1, \
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.num_threads_rx = UEC_NUM_OF_THREADS_1, \
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.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
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.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
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.tx_bd_ring_len = 16, \
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.rx_bd_ring_len = 16, \
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.phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
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.enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
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.speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
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}
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|
typedef struct uec_info {
|
ucc_fast_info_t uf_info;
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uec_num_of_threads_e num_threads_tx;
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uec_num_of_threads_e num_threads_rx;
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unsigned int risc_tx;
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unsigned int risc_rx;
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u16 rx_bd_ring_len;
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u16 tx_bd_ring_len;
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u8 phy_address;
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phy_interface_t enet_interface_type;
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int speed;
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} uec_info_t;
|
|
/* UEC driver initialized info
|
*/
|
#define MAX_RXBUF_LEN 1536
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#define MAX_FRAME_LEN 1518
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#define MIN_FRAME_LEN 64
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#define MAX_DMA1_LEN 1520
|
#define MAX_DMA2_LEN 1520
|
|
/* UEC driver private struct
|
*/
|
typedef struct uec_private {
|
uec_info_t *uec_info;
|
ucc_fast_private_t *uccf;
|
struct eth_device *dev;
|
uec_t *uec_regs;
|
uec_mii_t *uec_mii_regs;
|
/* enet init command parameter */
|
uec_init_cmd_pram_t *p_init_enet_param;
|
u32 init_enet_param_offset;
|
/* Rx and Tx paramter */
|
uec_rx_global_pram_t *p_rx_glbl_pram;
|
u32 rx_glbl_pram_offset;
|
uec_tx_global_pram_t *p_tx_glbl_pram;
|
u32 tx_glbl_pram_offset;
|
uec_send_queue_mem_region_t *p_send_q_mem_reg;
|
u32 send_q_mem_reg_offset;
|
uec_thread_data_tx_t *p_thread_data_tx;
|
u32 thread_dat_tx_offset;
|
uec_thread_data_rx_t *p_thread_data_rx;
|
u32 thread_dat_rx_offset;
|
uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl;
|
u32 rx_bd_qs_tbl_offset;
|
/* BDs specific */
|
u8 *p_tx_bd_ring;
|
u32 tx_bd_ring_offset;
|
u8 *p_rx_bd_ring;
|
u32 rx_bd_ring_offset;
|
u8 *p_rx_buf;
|
u32 rx_buf_offset;
|
volatile qe_bd_t *txBd;
|
volatile qe_bd_t *rxBd;
|
/* Status */
|
int mac_tx_enabled;
|
int mac_rx_enabled;
|
int grace_stopped_tx;
|
int grace_stopped_rx;
|
int the_first_run;
|
/* PHY specific */
|
struct uec_mii_info *mii_info;
|
int oldspeed;
|
int oldduplex;
|
int oldlink;
|
} uec_private_t;
|
|
int uec_initialize(bd_t *bis, uec_info_t *uec_info);
|
int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num);
|
int uec_standard_init(bd_t *bis);
|
#endif /* __UEC_H__ */
|
