/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/gic.h>
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#include <config.h>
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#include "irq-internal.h"
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#define gicd_readl(offset) readl((void *)GICD_BASE + (offset))
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#define gicc_readl(offset) readl((void *)GICC_BASE + (offset))
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#define gicd_writel(v, offset) writel(v, (void *)GICD_BASE + (offset))
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#define gicc_writel(v, offset) writel(v, (void *)GICC_BASE + (offset))
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/* 64-bit write */
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#define gicd_writeq(v, offset) writeq(v, (void *)GICD_BASE + (offset))
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#define IRQ_REG_X4(irq) (4 * ((irq) / 4))
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#define IRQ_REG_X16(irq) (4 * ((irq) / 16))
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#define IRQ_REG_X32(irq) (4 * ((irq) / 32))
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#define IRQ_REG_X4_OFFSET(irq) ((irq) % 4)
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#define IRQ_REG_X16_OFFSET(irq) ((irq) % 16)
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#define IRQ_REG_X32_OFFSET(irq) ((irq) % 32)
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#define MPIDR_CPU_MASK 0xff
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#define IROUTER_IRM_SHIFT 31
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#define IROUTER_IRM_MASK 0x1
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#define gicd_irouter_val_from_mpidr(mpidr, irm) \
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((mpidr & ~(0xff << 24)) | \
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(irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT)
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typedef enum INT_TRIG {
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INT_LEVEL_TRIGGER,
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INT_EDGE_TRIGGER
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} eINT_TRIG;
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struct gic_dist_data {
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uint32_t ctlr;
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uint32_t icfgr[DIV_ROUND_UP(1020, 16)];
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uint32_t itargetsr[DIV_ROUND_UP(1020, 4)];
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uint32_t ipriorityr[DIV_ROUND_UP(1020, 4)];
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uint32_t igroupr[DIV_ROUND_UP(1020, 32)];
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uint32_t ispendr[DIV_ROUND_UP(1020, 32)];
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uint32_t isenabler[DIV_ROUND_UP(1020, 32)];
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};
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struct gic_cpu_data {
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uint32_t ctlr;
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uint32_t pmr;
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};
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static struct gic_dist_data gicd_save;
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static struct gic_cpu_data gicc_save;
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static inline void int_set_prio_filter(u32 priority)
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{
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gicc_writel(priority & 0xff, GICC_PMR);
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}
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static inline void int_enable_distributor(void)
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{
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u32 val;
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val = gicd_readl(GICD_CTLR);
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val |= 0x01;
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gicd_writel(val, GICD_CTLR);
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}
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static inline void int_disable_distributor(void)
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{
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u32 val;
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val = gicd_readl(GICD_CTLR);
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val &= ~0x01;
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gicd_writel(val, GICD_CTLR);
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}
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static inline void int_enable_secure_signal(void)
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{
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u32 val;
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val = gicc_readl(GICC_CTLR);
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val |= 0x01;
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gicc_writel(val, GICC_CTLR);
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}
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static inline void int_disable_secure_signal(void)
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{
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u32 val;
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val = gicc_readl(GICC_CTLR);
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val &= ~0x01;
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gicc_writel(val, GICC_CTLR);
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}
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static inline void int_enable_nosecure_signal(void)
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{
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u32 val;
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val = gicc_readl(GICC_CTLR);
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val |= 0x02;
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gicc_writel(val, GICC_CTLR);
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}
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static inline void int_disable_nosecure_signal(void)
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{
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u32 val;
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val = gicc_readl(GICC_CTLR);
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val &= ~0x02;
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gicc_writel(val, GICC_CTLR);
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}
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static int gic_irq_set_trigger(int irq, eINT_TRIG trig)
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{
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u32 val;
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if (trig == INT_LEVEL_TRIGGER) {
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val = gicd_readl(GICD_ICFGR + IRQ_REG_X16(irq));
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val &= ~(1 << (2 * IRQ_REG_X16_OFFSET(irq) + 1));
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gicd_writel(val, GICD_ICFGR + IRQ_REG_X16(irq));
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} else {
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val = gicd_readl(GICD_ICFGR + IRQ_REG_X16(irq));
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val |= (1 << (2 * IRQ_REG_X16_OFFSET(irq) + 1));
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gicd_writel(val, GICD_ICFGR + IRQ_REG_X16(irq));
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}
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return 0;
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}
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static int gic_irq_enable(int irq)
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{
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#ifdef CONFIG_GICV2
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u32 val, cpu_mask;
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u32 shift = (irq % 4) * 8;
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if (irq >= PLATFORM_GIC_MAX_IRQ)
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return -EINVAL;
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/* set enable */
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val = gicd_readl(GICD_ISENABLERn + IRQ_REG_X32(irq));
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val |= 1 << IRQ_REG_X32_OFFSET(irq);
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gicd_writel(val, GICD_ISENABLERn + IRQ_REG_X32(irq));
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/* set target */
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cpu_mask = 1 << (read_mpidr() & MPIDR_CPU_MASK);
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val = gicd_readl(GICD_ITARGETSRn + IRQ_REG_X4(irq));
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val &= ~(0xFF << shift);
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val |= (cpu_mask << shift);
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gicd_writel(val, GICD_ITARGETSRn + IRQ_REG_X4(irq));
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#else
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u32 val;
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u64 affinity_val;
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/* set enable */
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val = gicd_readl(GICD_ISENABLERn + IRQ_REG_X32(irq));
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val |= 1 << IRQ_REG_X32_OFFSET(irq);
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gicd_writel(val, GICD_ISENABLERn + IRQ_REG_X32(irq));
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/* set itouter(target) */
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affinity_val = gicd_irouter_val_from_mpidr(read_mpidr(), 0);
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gicd_writeq(affinity_val, GICD_IROUTERn + (irq << 3));
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#endif
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return 0;
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}
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static int gic_irq_disable(int irq)
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{
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gicd_writel(1 << IRQ_REG_X32_OFFSET(irq),
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GICD_ICENABLERn + IRQ_REG_X32(irq));
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return 0;
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}
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/*
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* irq_set_type - set the irq trigger type for an irq
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*
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* @irq: irq number
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* @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see asm/arch/irq.h
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*/
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static int gic_irq_set_type(int irq, unsigned int type)
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{
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unsigned int int_type;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_EDGE_FALLING:
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int_type = 0x1;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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case IRQ_TYPE_LEVEL_LOW:
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int_type = 0x0;
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break;
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default:
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return -EINVAL;
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}
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gic_irq_set_trigger(irq, int_type);
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return 0;
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}
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static void gic_irq_eoi(int irq)
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{
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#ifdef CONFIG_GICV2
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gicc_writel(irq, GICC_EOIR);
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#else
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asm volatile("msr " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq));
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asm volatile("msr " __stringify(ICC_DIR_EL1) ", %0" : : "r" ((u64)irq));
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isb();
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#endif
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}
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static int gic_irq_get(void)
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{
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#ifdef CONFIG_GICV2
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return gicc_readl(GICC_IAR) & 0x3fff; /* bit9 - bit0 */
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#else
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u64 irqstat;
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asm volatile("mrs %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
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return (u32)irqstat & 0x3ff;
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#endif
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}
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static int gic_irq_suspend(void)
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{
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int irq_nr, i, irq;
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#ifndef CONFIG_GICV2
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u32 reg;
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#endif
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/* irq nr */
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irq_nr = ((gicd_readl(GICD_TYPER) & 0x1f) + 1) * 32;
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if (irq_nr > 1020)
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irq_nr = 1020;
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/* GICC save */
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#ifdef CONFIG_GICV2
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gicc_save.ctlr = gicc_readl(GICC_CTLR);
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gicc_save.pmr = gicc_readl(GICC_PMR);
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#else
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asm volatile("mrs %0, " __stringify(ICC_CTLR_EL1) : "=r" (reg));
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gicc_save.ctlr = reg;
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asm volatile("mrs %0, " __stringify(ICC_PMR_EL1) : "=r" (reg));
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gicc_save.pmr = reg;
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#endif
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/* GICD save */
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gicd_save.ctlr = gicd_readl(GICD_CTLR);
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for (i = 0, irq = 0; irq < irq_nr; irq += 16)
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gicd_save.icfgr[i++] =
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gicd_readl(GICD_ICFGR + IRQ_REG_X16(irq));
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for (i = 0, irq = 0; irq < irq_nr; irq += 4)
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gicd_save.itargetsr[i++] =
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gicd_readl(GICD_ITARGETSRn + IRQ_REG_X4(irq));
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for (i = 0, irq = 0; irq < irq_nr; irq += 4)
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gicd_save.ipriorityr[i++] =
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gicd_readl(GICD_IPRIORITYRn + IRQ_REG_X4(irq));
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for (i = 0, irq = 0; irq < irq_nr; irq += 32)
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gicd_save.igroupr[i++] =
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gicd_readl(GICD_IGROUPRn + IRQ_REG_X32(irq));
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for (i = 0, irq = 0; irq < irq_nr; irq += 32)
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gicd_save.ispendr[i++] =
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gicd_readl(GICD_ISPENDRn + IRQ_REG_X32(irq));
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for (i = 0, irq = 0; irq < irq_nr; irq += 32)
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gicd_save.isenabler[i++] =
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gicd_readl(GICD_ISENABLERn + IRQ_REG_X32(irq));
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dsb();
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return 0;
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}
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static int gic_irq_resume(void)
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{
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int irq_nr, i, irq;
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#ifndef CONFIG_GICV2
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u32 reg;
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#endif
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irq_nr = ((gicd_readl(GICD_TYPER) & 0x1f) + 1) * 32;
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if (irq_nr > 1020)
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irq_nr = 1020;
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/* Disable ctrl register */
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#ifdef CONFIG_GICV2
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gicc_writel(0, GICC_CTLR);
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#else
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reg = 0;
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asm volatile("msr " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (reg));
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#endif
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gicd_writel(0, GICD_CTLR);
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dsb();
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/* Clear all interrupt */
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for (i = 0, irq = 0; irq < irq_nr; irq += 32)
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gicd_writel(0xffffffff,
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GICD_ICENABLERn + IRQ_REG_X32(irq));
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for (i = 0, irq = 0; irq < irq_nr; irq += 16)
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gicd_writel(gicd_save.icfgr[i++],
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GICD_ICFGR + IRQ_REG_X16(irq));
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for (i = 0, irq = 0; irq < irq_nr; irq += 4)
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gicd_writel(gicd_save.itargetsr[i++],
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GICD_ITARGETSRn + IRQ_REG_X4(irq));
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for (i = 0, irq = 0; irq < irq_nr; irq += 4)
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gicd_writel(gicd_save.ipriorityr[i++],
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GICD_IPRIORITYRn + IRQ_REG_X4(irq));
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for (i = 0, irq = 0; irq < irq_nr; irq += 32)
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gicd_writel(gicd_save.igroupr[i++],
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GICD_IGROUPRn + IRQ_REG_X32(irq));
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for (i = 0, irq = 0; irq < irq_nr; irq += 32)
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gicd_writel(gicd_save.isenabler[i++],
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GICD_ISENABLERn + IRQ_REG_X32(irq));
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for (i = 0, irq = 0; irq < irq_nr; irq += 32)
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gicd_writel(gicd_save.ispendr[i++],
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GICD_ISPENDRn + IRQ_REG_X32(irq));
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dsb();
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#ifdef CONFIG_GICV2
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gicc_writel(gicc_save.pmr, GICC_PMR);
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gicc_writel(gicc_save.ctlr, GICC_CTLR);
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#else
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reg = gicc_save.pmr;
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asm volatile("msr " __stringify(ICC_PMR_EL1) ", %0" : : "r" (reg));
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reg = gicc_save.ctlr;
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asm volatile("msr " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (reg));
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#endif
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gicd_writel(gicd_save.ctlr, GICD_CTLR);
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dsb();
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#if defined(CONFIG_GICV3)
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asm volatile("msr " __stringify(ICC_IGRPEN1_EL1) ", %0" : : "r" (1));
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dsb();
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#endif
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return 0;
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}
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/**************************************regs save and resume**************************/
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static int gic_irq_init(void)
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{
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/* GICV3 done in: arch/arm/cpu/armv8/start.S */
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#ifdef CONFIG_GICV2
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u32 val;
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/*
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* If system boot without Miniloader:
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* "Maskrom => Trust(optional) => U-Boot"
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*
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* IRQ_USB_OTG must be acked by GICC_EIO due to maskrom jumps to the
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* U-Boot in its USB interrupt. Without this ack, the GICC_IAR always
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* return a spurious interrupt ID 1023 for USB OTG interrupt.
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*/
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#ifdef IRQ_USB_OTG
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gicc_writel(IRQ_USB_OTG, GICC_EOIR);
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#endif
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/* disable gicc and gicd */
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gicc_writel(0, GICC_CTLR);
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gicd_writel(0, GICD_CTLR);
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/* disable interrupt */
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gicd_writel(0xffffffff, GICD_ICENABLERn + 0);
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gicd_writel(0xffffffff, GICD_ICENABLERn + 4);
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gicd_writel(0xffffffff, GICD_ICENABLERn + 8);
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gicd_writel(0xffffffff, GICD_ICENABLERn + 12);
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val = gicd_readl(GICD_ICFGR + 12);
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val &= ~(1 << 1);
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gicd_writel(val, GICD_ICFGR + 12);
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/* set interrupt priority threhold min: 256 */
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int_set_prio_filter(0xff);
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int_enable_secure_signal();
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int_enable_nosecure_signal();
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int_enable_distributor();
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#endif
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return 0;
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}
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static struct irq_chip gic_irq_chip = {
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.name = "gic-irq-chip",
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.irq_init = gic_irq_init,
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.irq_suspend = gic_irq_suspend,
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.irq_resume = gic_irq_resume,
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.irq_get = gic_irq_get,
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.irq_enable = gic_irq_enable,
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.irq_disable = gic_irq_disable,
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.irq_eoi = gic_irq_eoi,
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.irq_set_type = gic_irq_set_type,
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};
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struct irq_chip *arch_gic_get_irqchip(void)
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{
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return &gic_irq_chip;
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}
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