/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _S3C24X0_I2C_H
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#define _S3C24X0_I2C_H
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struct s3c24x0_i2c {
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u32 iiccon;
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u32 iicstat;
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u32 iicadd;
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u32 iicds;
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u32 iiclc;
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};
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struct exynos5_hsi2c {
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u32 usi_ctl;
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u32 usi_fifo_ctl;
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u32 usi_trailing_ctl;
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u32 usi_clk_ctl;
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u32 usi_clk_slot;
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u32 spi_ctl;
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u32 uart_ctl;
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u32 res1;
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u32 usi_int_en;
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u32 usi_int_stat;
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u32 usi_modem_stat;
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u32 usi_error_stat;
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u32 usi_fifo_stat;
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u32 usi_txdata;
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u32 usi_rxdata;
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u32 res2;
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u32 usi_conf;
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u32 usi_auto_conf;
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u32 usi_timeout;
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u32 usi_manual_cmd;
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u32 usi_trans_status;
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u32 usi_timing_hs1;
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u32 usi_timing_hs2;
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u32 usi_timing_hs3;
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u32 usi_timing_fs1;
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u32 usi_timing_fs2;
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u32 usi_timing_fs3;
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u32 usi_timing_sla;
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u32 i2c_addr;
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};
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struct s3c24x0_i2c_bus {
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bool active; /* port is active and available */
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int node; /* device tree node */
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int bus_num; /* i2c bus number */
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struct s3c24x0_i2c *regs;
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struct exynos5_hsi2c *hsregs;
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int is_highspeed; /* High speed type, rather than I2C */
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unsigned clock_frequency;
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int id;
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unsigned clk_cycle;
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unsigned clk_div;
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};
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#define I2C_WRITE 0
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#define I2C_READ 1
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#define I2C_OK 0
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#define I2C_NOK 1
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#define I2C_NACK 2
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#define I2C_NOK_LA 3 /* Lost arbitration */
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#define I2C_NOK_TOUT 4 /* time out */
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/* S3C I2C Controller bits */
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#define I2CSTAT_BSY 0x20 /* Busy bit */
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#define I2CSTAT_NACK 0x01 /* Nack bit */
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#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
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#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
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#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
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#define I2C_MODE_MR 0x80 /* Master Receive Mode */
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#define I2C_START_STOP 0x20 /* START / STOP */
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#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
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#define I2C_TIMEOUT_MS 10 /* 10 ms */
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#endif /* _S3C24X0_I2C_H */
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