/*
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* (C) Copyright 2015 Xilinx, Inc,
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ZYNQMPPL_H_
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#define _ZYNQMPPL_H_
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#include <xilinx.h>
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#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018
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#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016
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#define ZYNQMP_FPGA_OP_INIT (1 << 0)
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#define ZYNQMP_FPGA_OP_LOAD (1 << 1)
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#define ZYNQMP_FPGA_OP_DONE (1 << 2)
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#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
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#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \
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ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
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#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
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#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
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extern struct xilinx_fpga_op zynqmp_op;
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#define XILINX_ZYNQMP_DESC \
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{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
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#endif /* _ZYNQMPPL_H_ */
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