/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ROCKCHIP_IR_H__
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#define __ROCKCHIP_IR_H__
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#include <linux/bitops.h>
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/* Registers */
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/* High polarity cycles */
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#define PWM_HPR_REG 0x04
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/* Low polarity cycles */
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#define PWM_LPR_REG 0x08
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/* PWM Control */
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#define PWM_CTL_REG 0x0c
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/* Enable */
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#define REG_CTL_EN BIT(0)
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/* capture mode */
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#define REG_CTL_MD BIT(2)
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/* Interrupt Status */
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#define PWM_STA_REG(id) ((4 - (id)) * 0x10)
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#define PWM_CH_POL(id) BIT(id + 8)
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/* Interrupt Enable */
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#define PWM_INT_REG(id) ((4 - (id)) * 0x14)
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#define PWM_CH_INT(id) BIT(id)
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/* NEC IR Pulse/Space protocol */
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#define NEC_NBITS 32
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#define NEC_UNIT 562500 /* ns */
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#define NEC_HEADER_PULSE (16 * NEC_UNIT)
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#define NEC_HEADER_SPACE (8 * NEC_UNIT)
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#define NEC_BIT_PULSE (1 * NEC_UNIT)
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#define NEC_BIT_0_SPACE (1 * NEC_UNIT)
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#define NEC_BIT_1_SPACE (3 * NEC_UNIT)
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#define TO_US(duration) ((duration) / 1000)
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#define TO_STR(is_pulse) ((is_pulse) ? "pulse" : "space")
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#define MAX_NUM_KEYS 60
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enum nec_state {
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STATE_INACTIVE,
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STATE_HEADER_SPACE,
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STATE_BIT_PULSE,
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STATE_BIT_SPACE,
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};
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struct rockchip_ir_priv {
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fdt_addr_t base;
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ulong freq;
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ulong period;
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int id;
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int num;
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int keycode;
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int repeat;
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};
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struct ir_raw_event {
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u32 duration;
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unsigned pulse:1;
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};
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struct nec_dec {
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int state;
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unsigned count;
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u32 bits;
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};
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struct rc_map_table {
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u32 scancode;
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u32 keycode;
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};
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struct rc_map {
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u32 usercode;
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u32 nbuttons;
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struct rc_map_table scan[MAX_NUM_KEYS];
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};
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/* macros for IR decoders */
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static inline bool eq_margin(unsigned d1, unsigned d2, unsigned margin)
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{
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return ((d1 > (d2 - margin)) && (d1 < (d2 + margin)));
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}
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#endif /* __ROCKCHIP_IR_H__ */
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