/*
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* This is from the ARM TF Project,
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* Repository: https://github.com/ARM-software/arm-trusted-firmware.git
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* File: include/common/bl_common.h
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* Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights
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* reserved.
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* Copyright (C) 2016-2017 Rockchip Electronic Co.,Ltd
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __BL_COMMON_H__
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#define __BL_COMMON_H__
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#define ATF_PARAM_EP 0x01
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#define ATF_PARAM_IMAGE_BINARY 0x02
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#define ATF_PARAM_BL31 0x03
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#define ATF_VERSION_1 0x01
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#define ATF_EP_SECURE 0x0
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#define ATF_EP_NON_SECURE 0x1
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#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \
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(_p)->h.type = (uint8_t)(_type); \
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(_p)->h.version = (uint8_t)(_ver); \
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(_p)->h.size = (uint16_t)sizeof(*_p); \
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(_p)->h.attr = (uint32_t)(_attr) ; \
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} while (0)
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/* ARM64 */
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#define MODE_RW_SHIFT 0x4
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#define MODE_RW_MASK 0x1
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#define MODE_RW_64 0x0
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#define MODE_RW_32 0x1
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#define MODE_EL_SHIFT 0x2
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#define MODE_EL_MASK 0x3
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#define MODE_EL3 0x3
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#define MODE_EL2 0x2
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#define MODE_EL1 0x1
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#define MODE_EL0 0x0
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#define MODE_SP_SHIFT 0x0
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#define MODE_SP_MASK 0x1
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#define MODE_SP_EL0 0x0
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#define MODE_SP_ELX 0x1
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#define SPSR_DAIF_SHIFT 6
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#define SPSR_DAIF_MASK 0x0f
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#define SPSR_64(el, sp, daif) \
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(MODE_RW_64 << MODE_RW_SHIFT | \
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((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \
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((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \
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((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
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#define SPSR_FIQ (1 << 6)
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#define SPSR_IRQ (1 << 7)
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#define SPSR_SERROR (1 << 8)
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#define SPSR_DEBUG (1 << 9)
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#define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG)
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#define DAIF_FIQ_BIT (1<<0)
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#define DAIF_IRQ_BIT (1<<1)
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#define DAIF_ABT_BIT (1<<2)
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#define DAIF_DBG_BIT (1<<3)
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#define DISABLE_ALL_EXECPTIONS \
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(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
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/* ARM */
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#define MODE32_SHIFT 0
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#define MODE32_MASK 0x1f
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#define MODE32_svc 0x13
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#define SPSR_FIQ_BIT (1 << 0)
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#define SPSR_IRQ_BIT (1 << 1)
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#define SPSR_ABT_BIT (1 << 2)
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#define SPSR_AIF_SHIFT 6
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#define SPSR_AIF_MASK 0x7
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#define EP_EE_LITTLE 0x0
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#define SPSR_E_SHIFT 9
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#define SPSR_E_MASK 0x1
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#define SPSR_T_SHIFT 5
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#define SPSR_T_MASK 0x1
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#define SPSR_T_ARM 0
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#define DISABLE_ALL_EXECPTIONS_32 \
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(SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
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#define SPSR_32(mode, isa, endian, aif) \
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(MODE_RW_32 << MODE_RW_SHIFT | \
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((mode) & MODE32_MASK) << MODE32_SHIFT | \
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((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
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((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
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((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
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#ifndef __ASSEMBLY__
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/*******************************************************************************
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* Structure used for telling the next BL how much of a particular type of
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* memory is available for its use and how much is already used.
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******************************************************************************/
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struct aapcs64_params {
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unsigned long arg0;
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unsigned long arg1;
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unsigned long arg2;
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unsigned long arg3;
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unsigned long arg4;
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unsigned long arg5;
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unsigned long arg6;
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unsigned long arg7;
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};
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/***************************************************************************
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* This structure provides version information and the size of the
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* structure, attributes for the structure it represents
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***************************************************************************/
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struct param_header {
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uint8_t type; /* type of the structure */
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uint8_t version; /* version of this structure */
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uint16_t size; /* size of this structure in bytes */
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uint32_t attr; /* attributes: unused bits SBZ */
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};
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/*****************************************************************************
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* This structure represents the superset of information needed while
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* switching exception levels. The only two mechanisms to do so are
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* ERET & SMC. Security state is indicated using bit zero of header
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* attribute
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* NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
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* of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
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* processing SMC to jump to BL31.
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*****************************************************************************/
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struct entry_point_info {
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struct param_header h;
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uintptr_t pc;
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uint32_t spsr;
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struct aapcs64_params args;
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};
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/*****************************************************************************
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* Image info binary provides information from the image loader that
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* can be used by the firmware to manage available trusted RAM.
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* More advanced firmware image formats can provide additional
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* information that enables optimization or greater flexibility in the
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* common firmware code
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*****************************************************************************/
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struct atf_image_info {
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struct param_header h;
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uintptr_t image_base; /* physical address of base of image */
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uint32_t image_size; /* bytes read from image file */
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};
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/*****************************************************************************
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* The image descriptor struct definition.
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*****************************************************************************/
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struct image_desc {
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/* Contains unique image id for the image. */
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unsigned int image_id;
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/*
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* This member contains Image state information.
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* Refer IMAGE_STATE_XXX defined above.
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*/
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unsigned int state;
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uint32_t copied_size; /* image size copied in blocks */
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struct atf_image_info atf_image_info;
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struct entry_point_info ep_info;
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};
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/*******************************************************************************
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* This structure represents the superset of information that can be passed to
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* BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
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* populated only if BL2 detects its presence. A pointer to a structure of this
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* type should be passed in X0 to BL31's cold boot entrypoint.
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*
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* Use of this structure and the X0 parameter is not mandatory: the BL31
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* platform code can use other mechanisms to provide the necessary information
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* about BL32 and BL33 to the common and SPD code.
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*
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* BL31 image information is mandatory if this structure is used. If either of
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* the optional BL32 and BL33 image information is not provided, this is
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* indicated by the respective image_info pointers being zero.
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******************************************************************************/
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struct bl31_params {
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struct param_header h;
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struct atf_image_info *bl31_image_info;
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struct entry_point_info *bl32_ep_info;
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struct atf_image_info *bl32_image_info;
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struct entry_point_info *bl33_ep_info;
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struct atf_image_info *bl33_image_info;
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};
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/*******************************************************************************
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* This structure represents the superset of information that is passed to
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* BL31, e.g. while passing control to it from BL2, bl31_params
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* and other platform specific params
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******************************************************************************/
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struct bl2_to_bl31_params_mem {
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struct bl31_params bl31_params;
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struct atf_image_info bl31_image_info;
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struct atf_image_info bl32_image_info;
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struct atf_image_info bl33_image_info;
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struct entry_point_info bl33_ep_info;
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struct entry_point_info bl32_ep_info;
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struct entry_point_info bl31_ep_info;
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};
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#endif /*__ASSEMBLY__*/
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#endif /* __BL_COMMON_H__ */
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