/*
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* Copyright (c) 2011-2013 Xilinx Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/microblaze_intc.h>
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#include <asm/processor.h>
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#include <watchdog.h>
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#define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */
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#define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */
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#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/
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#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */
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struct watchdog_regs {
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u32 twcsr0; /* 0x0 */
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u32 twcsr1; /* 0x4 */
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u32 tbr; /* 0x8 */
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};
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static struct watchdog_regs *watchdog_base =
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(struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR;
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void hw_watchdog_reset(void)
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{
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u32 reg;
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/* Read the current contents of TCSR0 */
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reg = readl(&watchdog_base->twcsr0);
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/* Clear the watchdog WDS bit */
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if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
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writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0);
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}
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void hw_watchdog_disable(void)
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{
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u32 reg;
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/* Read the current contents of TCSR0 */
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reg = readl(&watchdog_base->twcsr0);
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writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0);
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writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
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puts("Watchdog disabled!\n");
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}
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static void hw_watchdog_isr(void *arg)
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{
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hw_watchdog_reset();
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}
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void hw_watchdog_init(void)
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{
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int ret;
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writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
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&watchdog_base->twcsr0);
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writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
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ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ,
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hw_watchdog_isr, NULL);
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if (ret)
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puts("Watchdog IRQ registration failed.");
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}
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