// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <dm/root.h>
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#include <dt-structs.h>
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#include <regmap.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sdram_rv1108.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/sdram.h>
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struct dram_info info;
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struct rockchip_dmc_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rv1108_dmc dtplat;
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#else
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struct sdram_params params;
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#endif
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struct regmap *map;
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};
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void enable_ddr_io_ret(struct dram_info *priv)
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{
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writel(DDR_IO_RET_EN, &priv->pmu->sft_con);
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rk_clrsetreg(&priv->pmu_grf->soc_con[0],
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DDRPHY_BUFFEREN_CORE_MASK,
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DDRPHY_BUFFEREN_CORE_EN);
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}
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void rkdclk_init(struct dram_info *priv,
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struct sdram_params *params_priv)
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{
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rk_clrsetreg(&priv->cru->pll[1].con3, WORK_MODE_MASK,
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WORK_MODE_SLOW << WORK_MODE_SHIFT);
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rk_clrsetreg(&priv->cru->pll[1].con3, GLOBAL_POWER_DOWN_MASK,
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GLOBAL_POWER_DOWN << GLOBAL_POWER_DOWN_SHIFT);
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rk_clrsetreg(&priv->cru->pll[1].con3, DSMPD_MASK,
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INTEGER_MODE << DSMPD_SHIFT);
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rk_clrsetreg(&priv->cru->pll[1].con0, FBDIV_MASK,
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params_priv->dpll_init_cfg.fbdiv << FBDIV_SHIFT);
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rk_clrsetreg(&priv->cru->pll[1].con1,
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POSTDIV2_MASK | POSTDIV1_MASK | REFDIV_MASK,
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params_priv->dpll_init_cfg.postdiv2 << POSTDIV2_SHIFT |
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params_priv->dpll_init_cfg.postdiv1 << POSTDIV1_SHIFT |
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params_priv->dpll_init_cfg.refdiv << REFDIV_SHIFT);
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rk_clrsetreg(&priv->cru->pll[1].con3, GLOBAL_POWER_DOWN_MASK,
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GLOBAL_POWER_UP << GLOBAL_POWER_DOWN_SHIFT);
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while (!(readl(&priv->cru->pll[1].con2) & (1u << LOCK_STA_SHIFT)))
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udelay(1);
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rk_clrsetreg(&priv->cru->clksel_con[4], CLK_DDR_PLL_SEL_MASK |
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CLK_DDR_DIV_CON_MASK, 0 << CLK_DDR_PLL_SEL_SHIFT |
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0 << CLK_DDR_DIV_CON_SHIFT);
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rk_clrsetreg(&priv->cru->pll[1].con3, WORK_MODE_MASK,
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WORK_MODE_NORMAL << WORK_MODE_SHIFT);
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}
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void phy_pctrl_reset_cru(struct dram_info *priv)
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{
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rk_clrsetreg(&priv->cru->softrst_con[2], DDRUPCTL_PSRSTN_REQ_MASK |
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DDRUPCTL_NSRSTN_REQ_MASK,
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DDRUPCTL_PSRSTN_REQ << DDRUPCTL_PSRSTN_REQ_SHIFT |
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DDRUPCTL_NSRSTN_REQ << DDRUPCTL_NSRSTN_REQ_SHIFT);
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rk_clrsetreg(&priv->cru->softrst_con[1],
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DDRPHY_SRSTN_CLKDIV_REQ_MASK | DDRPHY_SRSTN_REQ_MASK |
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DDRPHY_PSRSTN_REQ_MASK,
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DDRPHY_SRSTN_CLKDIV_REQ << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT |
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DDRPHY_SRSTN_REQ << DDRPHY_SRSTN_REQ_SHIFT |
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DDRPHY_PSRSTN_REQ << DDRPHY_PSRSTN_REQ_SHIFT);
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udelay(10);
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rk_clrsetreg(&priv->cru->softrst_con[1],
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DDRPHY_SRSTN_CLKDIV_REQ_MASK | DDRPHY_SRSTN_REQ_MASK |
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DDRPHY_PSRSTN_REQ_MASK,
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DDRPHY_SRSTN_CLKDIV_DIS << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT |
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DDRPHY_PSRSTN_DIS << DDRPHY_PSRSTN_REQ_SHIFT |
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DDRPHY_SRSTN_DIS << DDRPHY_SRSTN_REQ_SHIFT);
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udelay(10);
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rk_clrsetreg(&priv->cru->softrst_con[2], DDRUPCTL_PSRSTN_REQ_MASK |
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DDRUPCTL_NSRSTN_REQ_MASK,
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DDRUPCTL_PSRSTN_DIS << DDRUPCTL_PSRSTN_REQ_SHIFT |
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DDRUPCTL_NSRSTN_DIS << DDRUPCTL_NSRSTN_REQ_SHIFT);
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udelay(10);
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}
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void pctl_cfg_grf(struct dram_info *priv,
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struct sdram_params *params_priv)
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{
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writel(RK_SETBITS(MSCH_MAINDDR3 | MSCH_MAINPARTIALPOP),
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&priv->grf->soc_con0);
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}
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void ddr_msch_cfg(struct dram_info *priv,
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struct sdram_params *params_priv)
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{
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writel((readl(&priv->service_msch->ddrtiming) & BWRATIO_HALF_BW) |
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params_priv->ddr_timing_t.noc_timing.d32,
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&priv->service_msch->ddrtiming);
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writel(params_priv->ddr_timing_t.readlatency,
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&priv->service_msch->readlatency);
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writel(params_priv->ddr_timing_t.activate.d32,
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&priv->service_msch->activate);
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writel(params_priv->ddr_timing_t.devtodev,
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&priv->service_msch->devtodev);
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}
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void ddr_msch_cfg_rbc(struct sdram_params *params_priv,
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struct dram_info *priv)
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{
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int i = 0;
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if (params_priv->ddr_config_t.col == 10)
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i = 2;
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else
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i = 3;
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writel(i, &priv->service_msch->ddrconf);
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}
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void ddr_phy_skew_cfg(struct dram_info *priv)
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{
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}
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void set_ds_odt(struct dram_info *priv,
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struct sdram_params *params_priv)
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{
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/* set phy drive impedance */
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writel(PHY_RON_RTT_34OHM, &priv->phy->phy_reg11);
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clrsetbits_le32(&priv->phy->phy_reg12, CMD_PRCOMP_MASK,
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PHY_RON_RTT_34OHM << CMD_PRCOMP_SHIFT);
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writel(PHY_RON_RTT_45OHM, &priv->phy->phy_reg16);
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writel(PHY_RON_RTT_45OHM, &priv->phy->phy_reg18);
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writel(PHY_RON_RTT_34OHM, &priv->phy->phy_reg20);
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writel(PHY_RON_RTT_34OHM, &priv->phy->phy_reg2f);
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writel(PHY_RON_RTT_34OHM, &priv->phy->phy_reg30);
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writel(PHY_RON_RTT_34OHM, &priv->phy->phy_reg3f);
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/*set phy odt*/
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writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg21);
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writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg2e);
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writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg31);
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writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg3e);
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}
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void ddr_phy_dqs_rx_dll_cfg(struct dram_info *priv, u32 freq)
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{
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/* 45 degree delay */
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writel(LEFT_CHN_A_READ_DQS_45_DELAY, &priv->phy->phy_reg28);
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writel(RIGHT_CHN_A_READ_DQS_45_DELAY, &priv->phy->phy_reg38);
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}
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void ddr_msch_get_max_col(struct dram_info *priv,
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struct ddr_schedule *sch_priv)
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{
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writel(1, &priv->service_msch->ddrconf);
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sch_priv->col = 11;
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sch_priv->bank = 3;
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}
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void ddr_msch_get_max_row(struct dram_info *priv,
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struct ddr_schedule *sch_priv)
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{
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writel(1, &priv->service_msch->ddrconf);
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sch_priv->row = 16;
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sch_priv->col = 11;
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sch_priv->bank = 3;
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}
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void *get_base_addr(unsigned int *reg, unsigned int offset)
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{
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u32 p = *(reg + 2 * offset);
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return (void *)p;
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}
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void modify_data_training(struct dram_info *priv,
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struct sdram_params *params_priv)
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{
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printascii("REGFB: 0x");
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printhex8(readl(&priv->phy->phy_regfb));
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printascii(", 0x");
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printhex8(readl(&priv->phy->phy_regfc));
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printascii("\n");
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}
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int check_rd_gate(struct dram_info *priv)
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{
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return 0;
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}
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void enable_low_power(struct dram_info *priv,
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struct sdram_params *params_priv)
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{
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move_to_config_state(priv);
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clrsetbits_le32(&priv->pctl->mcfg, PD_IDLE_MASK,
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PD_IDLE << PD_IDLE_SHIFT);
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clrsetbits_le32(&priv->pctl->mcfg1,
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SR_IDLE_MASK | HW_EXIT_IDLE_EN_MASK,
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SR_IDLE | HW_EXIT_IDLE_EN);
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/* uPCTL in low_power status because of auto self-refresh */
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writel(GO_STATE, &priv->pctl->sctl);
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}
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void get_ddr_param(struct dram_info *sdram_priv,
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struct ddr_param *ddr_param)
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{
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size_t ram_size =
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rockchip_sdram_size((phys_addr_t)&sdram_priv->grf->os_reg2);
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ddr_param->count = 1;
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ddr_param->para[0] = CONFIG_SYS_SDRAM_BASE;
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ddr_param->para[1] = ram_size;
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}
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int sdram_init(void)
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{
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int ret;
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struct ddr_param ddr_param;
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struct dram_info *sdram_priv = &info;
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struct driver_info *info =
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ll_entry_start(struct driver_info, driver_info);
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rv1108_dmc *dtplat = (void *)info->platdata;
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struct sdram_params *params = (void *)dtplat->rockchip_sdram_params;
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sdram_priv->pctl = get_base_addr((void *)dtplat->reg, 0);
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sdram_priv->phy = get_base_addr((void *)dtplat->reg, 1);
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sdram_priv->service_msch = get_base_addr((void *)dtplat->reg, 2);
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sdram_priv->grf = get_base_addr((void *)dtplat->reg, 3);
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sdram_priv->pmu_grf = get_base_addr((void *)dtplat->reg, 4);
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sdram_priv->cru = get_base_addr((void *)dtplat->reg, 5);
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sdram_priv->pmu = get_base_addr((void *)dtplat->reg, 6);
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#else
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struct sdram_params *params = (void *)info->platdata;
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#endif
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ret = rv1108_sdram_init(sdram_priv, params);
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if (ret)
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debug("rv1108_sdram_init() fail!");
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get_ddr_param(sdram_priv, &ddr_param);
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rockchip_setup_ddr_param(&ddr_param);
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return ret;
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}
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