// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2022 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <i2c.h>
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#include <max96755f.h>
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#include <dm/pinctrl.h>
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struct config_desc {
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u16 reg;
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u8 mask;
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u8 val;
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};
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struct function_desc {
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const char *name;
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const char **group_names;
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int num_group_names;
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u8 gpio_out_dis:1;
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u8 gpio_tx_en:1;
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u8 gpio_rx_en:1;
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u8 oldi:1;
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u8 gpio_tx_id;
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u8 gpio_rx_id;
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};
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struct group_desc {
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const char *name;
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int *pins;
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int num_pins;
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const struct config_desc *configs;
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int num_configs;
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};
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struct pin_desc {
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unsigned int number;
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const char *name;
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};
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static const struct pin_desc max96755f_pins[] = {
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{0, "gpio0"},
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{1, "gpio1"},
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{2, "gpio2"},
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{3, "gpio3"},
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{4, "gpio4"},
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{5, "gpio5"},
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{6, "gpio6"},
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{7, "gpio7"},
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{8, "gpio8"},
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{9, "gpio9"},
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{10, "gpio10"},
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{11, "gpio11"},
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{12, "gpio12"},
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{13, "gpio13"},
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{14, "gpio14"},
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{15, "gpio15"},
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{16, "gpio16"},
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{17, "gpio17"},
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{18, "gpio18"},
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{19, "gpio19"},
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{20, "gpio20"},
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};
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static int gpio0_pins[] = {0};
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static int gpio1_pins[] = {1};
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static int gpio2_pins[] = {2};
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static int gpio3_pins[] = {3};
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static int gpio4_pins[] = {4};
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static int gpio5_pins[] = {5};
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static int gpio6_pins[] = {6};
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static int gpio7_pins[] = {7};
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static int gpio8_pins[] = {8};
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static int gpio9_pins[] = {9};
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static int gpio10_pins[] = {10};
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static int gpio11_pins[] = {11};
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static int gpio12_pins[] = {12};
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static int gpio13_pins[] = {13};
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static int gpio14_pins[] = {14};
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static int gpio15_pins[] = {15};
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static int gpio16_pins[] = {16};
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static int gpio17_pins[] = {17};
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static int gpio18_pins[] = {18};
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static int gpio19_pins[] = {19};
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static int gpio20_pins[] = {20};
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static int i2c_pins[] = {19, 20};
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static int uart_pins[] = {19, 20};
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#define GROUP_DESC(nm) \
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{ \
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.name = #nm, \
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.pins = nm ## _pins, \
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.num_pins = ARRAY_SIZE(nm ## _pins), \
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}
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#define GROUP_DESC_CONFIG(nm) \
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{ \
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.name = #nm, \
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.pins = nm ## _pins, \
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.num_pins = ARRAY_SIZE(nm ## _pins), \
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.configs = nm ## _configs, \
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.num_configs = ARRAY_SIZE(nm ## _configs), \
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}
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static const struct config_desc gpio0_configs[] = {
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{ 0x0005, LOCK_EN, 0 },
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{ 0x0048, LOC_MS_EN, 0},
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};
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static const struct config_desc gpio1_configs[] = {
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{ 0x0005, ERRB_EN, 0 },
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};
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static const struct config_desc gpio4_configs[] = {
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{ 0x070, SPI_EN, 0 },
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};
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static const struct config_desc gpio5_configs[] = {
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{ 0x006, RCLKEN, 0 },
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};
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static const struct config_desc gpio7_configs[] = {
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{ 0x0002, AUD_TX_EN_X, 0 },
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{ 0x0002, AUD_TX_EN_Y, 0 }
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};
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static const struct config_desc gpio8_configs[] = {
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{ 0x0002, AUD_TX_EN_X, 0 },
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{ 0x0002, AUD_TX_EN_Y, 0 }
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};
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static const struct config_desc gpio9_configs[] = {
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{ 0x0002, AUD_TX_EN_X, 0 },
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{ 0x0002, AUD_TX_EN_Y, 0 }
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};
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static const struct config_desc gpio10_configs[] = {
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{ 0x0001, IIC_2_EN, 0 },
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{ 0x0003, UART_2_EN, 0 },
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{ 0x0140, AUD_RX_EN, 0},
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};
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static const struct config_desc gpio11_configs[] = {
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{ 0x0001, IIC_2_EN, 0 },
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{ 0x0003, UART_2_EN, 0 },
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{ 0x0140, AUD_RX_EN, 0},
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};
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static const struct config_desc gpio12_configs[] = {
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{ 0x0140, AUD_RX_EN, 0 },
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};
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static const struct config_desc gpio13_configs[] = {
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{ 0x0005, PU_LF0, 0 },
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};
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static const struct config_desc gpio14_configs[] = {
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{ 0x0005, PU_LF1, 0 },
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};
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static const struct config_desc gpio15_configs[] = {
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{ 0x0005, PU_LF2, 0 },
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};
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static const struct config_desc gpio16_configs[] = {
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{ 0x0005, PU_LF3, 0 },
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};
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static const struct config_desc gpio17_configs[] = {
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{ 0x0001, IIC_1_EN, 0 },
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{ 0x0003, UART_1_EN, 0 },
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};
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static const struct config_desc gpio18_configs[] = {
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{ 0x0001, IIC_1_EN, 0 },
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{ 0x0003, UART_1_EN, 0 },
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};
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static const struct group_desc max96755f_groups[] = {
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GROUP_DESC_CONFIG(gpio0),
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GROUP_DESC_CONFIG(gpio1),
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GROUP_DESC(gpio2),
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GROUP_DESC(gpio3),
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GROUP_DESC_CONFIG(gpio4),
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GROUP_DESC_CONFIG(gpio5),
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GROUP_DESC(gpio6),
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GROUP_DESC_CONFIG(gpio7),
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GROUP_DESC_CONFIG(gpio8),
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GROUP_DESC_CONFIG(gpio9),
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GROUP_DESC_CONFIG(gpio10),
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GROUP_DESC_CONFIG(gpio11),
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GROUP_DESC_CONFIG(gpio12),
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GROUP_DESC_CONFIG(gpio13),
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GROUP_DESC_CONFIG(gpio14),
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GROUP_DESC_CONFIG(gpio15),
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GROUP_DESC_CONFIG(gpio16),
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GROUP_DESC_CONFIG(gpio17),
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GROUP_DESC_CONFIG(gpio18),
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GROUP_DESC(gpio19),
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GROUP_DESC(gpio20),
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GROUP_DESC(i2c),
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GROUP_DESC(uart),
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};
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static const char *gpio_groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
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"gpio6", "gpio7", "gpio8", "gpio9", "gpio10",
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"gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
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"gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
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};
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static const char *i2c_groups[] = { "i2c" };
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static const char *uart_groups[] = { "uart" };
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#define FUNCTION_DESC(fname, gname) \
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{ \
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.name = #fname, \
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.group_names = gname##_groups, \
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.num_group_names = ARRAY_SIZE(gname##_groups), \
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} \
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#define FUNCTION_DESC_GPIO_RX(id) \
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{ \
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.name = "GPIO_RX_"#id, \
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.group_names = gpio_groups, \
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.num_group_names = ARRAY_SIZE(gpio_groups), \
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.gpio_rx_en = 1, \
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.gpio_rx_id = id, \
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} \
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#define FUNCTION_DESC_GPIO_TX(id) \
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{ \
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.name = "GPIO_TX_"#id, \
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.group_names = gpio_groups, \
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.num_group_names = ARRAY_SIZE(gpio_groups), \
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.gpio_out_dis = 1, \
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.gpio_tx_en = 1, \
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.gpio_tx_id = id \
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} \
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#define FUNCTION_DESC_GPIO() \
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{ \
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.name = "GPIO", \
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.group_names = gpio_groups, \
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.num_group_names = ARRAY_SIZE(gpio_groups), \
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} \
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static const struct function_desc max96755f_functions[] = {
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FUNCTION_DESC_GPIO_TX(0),
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FUNCTION_DESC_GPIO_TX(1),
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FUNCTION_DESC_GPIO_TX(2),
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FUNCTION_DESC_GPIO_TX(3),
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FUNCTION_DESC_GPIO_TX(4),
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FUNCTION_DESC_GPIO_TX(5),
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FUNCTION_DESC_GPIO_TX(6),
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FUNCTION_DESC_GPIO_TX(7),
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FUNCTION_DESC_GPIO_TX(8),
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FUNCTION_DESC_GPIO_TX(9),
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FUNCTION_DESC_GPIO_TX(10),
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FUNCTION_DESC_GPIO_TX(11),
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FUNCTION_DESC_GPIO_TX(12),
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FUNCTION_DESC_GPIO_TX(13),
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FUNCTION_DESC_GPIO_TX(14),
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FUNCTION_DESC_GPIO_TX(15),
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FUNCTION_DESC_GPIO_TX(16),
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FUNCTION_DESC_GPIO_TX(17),
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FUNCTION_DESC_GPIO_TX(18),
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FUNCTION_DESC_GPIO_TX(19),
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FUNCTION_DESC_GPIO_TX(20),
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FUNCTION_DESC_GPIO_RX(0),
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FUNCTION_DESC_GPIO_RX(1),
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FUNCTION_DESC_GPIO_RX(2),
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FUNCTION_DESC_GPIO_RX(3),
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FUNCTION_DESC_GPIO_RX(4),
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FUNCTION_DESC_GPIO_RX(5),
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FUNCTION_DESC_GPIO_RX(6),
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FUNCTION_DESC_GPIO_RX(7),
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FUNCTION_DESC_GPIO_RX(8),
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FUNCTION_DESC_GPIO_RX(9),
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FUNCTION_DESC_GPIO_RX(10),
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FUNCTION_DESC_GPIO_RX(11),
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FUNCTION_DESC_GPIO_RX(12),
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FUNCTION_DESC_GPIO_RX(13),
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FUNCTION_DESC_GPIO_RX(14),
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FUNCTION_DESC_GPIO_RX(15),
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FUNCTION_DESC_GPIO_RX(16),
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FUNCTION_DESC_GPIO_RX(17),
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FUNCTION_DESC_GPIO_RX(18),
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FUNCTION_DESC_GPIO_RX(19),
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FUNCTION_DESC_GPIO_RX(20),
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FUNCTION_DESC_GPIO(),
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FUNCTION_DESC(I2C, i2c),
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FUNCTION_DESC(UART, uart),
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};
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static int max96755f_get_pins_count(struct udevice *dev)
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{
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return ARRAY_SIZE(max96755f_pins);
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}
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static const char *max96755f_get_pin_name(struct udevice *dev,
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unsigned int selector)
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{
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return max96755f_pins[selector].name;
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}
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static int max96755f_pinctrl_get_groups_count(struct udevice *dev)
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{
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return ARRAY_SIZE(max96755f_groups);
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}
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static const char *max96755f_pinctrl_get_group_name(struct udevice *dev,
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unsigned int selector)
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{
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return max96755f_groups[selector].name;
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}
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static int max96755f_pinctrl_get_functions_count(struct udevice *dev)
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{
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return ARRAY_SIZE(max96755f_functions);
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}
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static const char *max96755f_pinctrl_get_function_name(struct udevice *dev,
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unsigned int selector)
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{
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return max96755f_functions[selector].name;
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}
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static int
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max96755f_pinmux_set(struct udevice *dev, unsigned int group_selector,
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unsigned int func_selector)
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{
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const struct group_desc *grp = &max96755f_groups[group_selector];
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const struct function_desc *func = &max96755f_functions[func_selector];
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int i, ret;
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for (i = 0; i < grp->num_configs; i++) {
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const struct config_desc *config = &grp->configs[i];
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ret = dm_i2c_reg_clrset(dev->parent, config->reg, config->mask,
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config->val);
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if (ret < 0)
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return ret;
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}
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for (i = 0; i < grp->num_pins; i++) {
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ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(grp->pins[i]),
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GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN,
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FIELD_PREP(GPIO_OUT_DIS, func->gpio_out_dis) |
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FIELD_PREP(GPIO_RX_EN, func->gpio_rx_en) |
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FIELD_PREP(GPIO_TX_EN, func->gpio_tx_en));
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if (ret < 0)
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return ret;
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if (func->gpio_tx_en) {
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ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(grp->pins[i]),
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GPIO_TX_ID,
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FIELD_PREP(GPIO_TX_ID, func->gpio_tx_id));
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if (ret < 0)
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return ret;
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}
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if (func->gpio_rx_en) {
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ret = dm_i2c_reg_clrset(dev->parent,
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GPIO_C_REG(grp->pins[i]),
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GPIO_RX_ID,
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FIELD_PREP(GPIO_RX_ID, func->gpio_rx_id));
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if (ret < 0)
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return ret;
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}
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}
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return 0;
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}
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static const struct pinconf_param max96755f_pinconf_params[] = {
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{ "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
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{ "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
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{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
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{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 40000 },
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{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 40000 },
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};
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static int max96755f_pinconf_set(struct udevice *dev, unsigned int pin,
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unsigned int param, unsigned int arg)
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{
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u8 res_cfg;
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int ret;
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switch (param) {
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(pin), OUT_TYPE,
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FIELD_PREP(OUT_TYPE, 0));
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if (ret < 0)
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return ret;
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break;
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(pin), OUT_TYPE,
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FIELD_PREP(OUT_TYPE, 1));
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if (ret < 0)
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return ret;
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin),
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PULL_UPDN_SEL,
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FIELD_PREP(PULL_UPDN_SEL, 0));
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if (ret < 0)
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return ret;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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switch (arg) {
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case 40000:
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res_cfg = 0;
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break;
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case 1000000:
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res_cfg = 1;
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break;
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default:
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return -EINVAL;
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}
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ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin), RES_CFG,
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FIELD_PREP(RES_CFG, res_cfg));
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if (ret < 0)
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return ret;
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ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin),
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PULL_UPDN_SEL,
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FIELD_PREP(PULL_UPDN_SEL, 1));
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if (ret < 0)
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return ret;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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switch (arg) {
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case 40000:
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res_cfg = 0;
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break;
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case 1000000:
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res_cfg = 1;
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break;
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default:
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return -EINVAL;
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}
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ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin), RES_CFG,
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FIELD_PREP(RES_CFG, res_cfg));
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if (ret < 0)
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return ret;
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ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin),
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PULL_UPDN_SEL,
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FIELD_PREP(PULL_UPDN_SEL, 2));
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if (ret < 0)
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return ret;
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break;
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case PIN_CONFIG_OUTPUT:
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ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin),
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GPIO_OUT_DIS | GPIO_OUT,
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FIELD_PREP(GPIO_OUT_DIS, 0) |
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FIELD_PREP(GPIO_OUT, arg));
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if (ret < 0)
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return ret;
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break;
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default:
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dev_err(dev, "unsupported configuration parameter %u\n", param);
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return -ENOTSUPP;
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}
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return 0;
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}
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static const struct pinctrl_ops max96755f_pinctrl_ops = {
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.get_pins_count = max96755f_get_pins_count,
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.get_pin_name = max96755f_get_pin_name,
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.get_groups_count = max96755f_pinctrl_get_groups_count,
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.get_group_name = max96755f_pinctrl_get_group_name,
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.get_functions_count = max96755f_pinctrl_get_functions_count,
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.get_function_name = max96755f_pinctrl_get_function_name,
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.set_state = pinctrl_generic_set_state,
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.pinmux_set = max96755f_pinmux_set,
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.pinmux_group_set = max96755f_pinmux_set,
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.pinconf_num_params = ARRAY_SIZE(max96755f_pinconf_params),
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.pinconf_params = max96755f_pinconf_params,
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.pinconf_set = max96755f_pinconf_set,
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};
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static const struct udevice_id max96755f_pinctrl_of_match[] = {
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{ .compatible = "maxim,max96755f-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(max96755f_pinctrl) = {
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.name = "pinctrl-max96755f",
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.id = UCLASS_PINCTRL,
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.of_match = max96755f_pinctrl_of_match,
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.ops = &max96755f_pinctrl_ops,
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};
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