// SPDX-License-Identifier: GPL-2.0+
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/**
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*
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* Driver for ROCKCHIP RK630 Ethernet PHYs
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*
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* Copyright (c) 2020, Fuzhou Rockchip Electronics Co., Ltd
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*
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* David Wu <david.wu@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <misc.h>
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#include <phy.h>
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#define RK630_PHY_ID 0x00441400
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/* PAGE 0 */
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#define REG_MMD_ACCESS_CONTROL 0x0d
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#define REG_MMD_ACCESS_DATA_ADDRESS 0x0e
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#define REG_INTERRUPT_STATUS 0X10
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#define REG_INTERRUPT_MASK 0X11
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#define REG_GLOBAL_CONFIGURATION 0X13
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#define REG_MAC_ADDRESS0 0x16
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#define REG_MAC_ADDRESS1 0x17
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#define REG_MAC_ADDRESS2 0x18
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#define REG_PAGE_SEL 0x1F
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/* PAGE 1 */
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#define REG_PAGE1_APS_CTRL 0x12
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#define REG_PAGE1_UAPS_CONFIGURE 0X13
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#define REG_PAGE1_EEE_CONFIGURE 0x17
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/* PAGE 2 */
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#define REG_PAGE2_AFE_CTRL 0x18
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/* PAGE 6 */
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#define REG_PAGE6_ADC_ANONTROL 0x10
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#define REG_PAGE6_GAIN_ANONTROL 0x12
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#define REG_PAGE6_AFE_RX_CTRL 0x13
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#define REG_PAGE6_AFE_TX_CTRL 0x14
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#define REG_PAGE6_AFE_DRIVER2 0x15
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#define REG_PAGE6_CP_CURRENT 0x17
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#define REG_PAGE6_ADC_OP_BIAS 0x18
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#define REG_PAGE6_RX_DECTOR 0x19
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#define REG_PAGE6_TX_MOS_DRV 0x1B
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#define REG_PAGE6_AFE_PDCW 0x1c
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/* PAGE 8 */
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#define REG_PAGE8_AFE_CTRL 0x18
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#define REG_PAGE8_AUTO_CAL 0x1d
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/*
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* Fixed address:
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* Addr: 1 --- RK630@S40
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* 2 --- RV1106@T22
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*/
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#define PHY_ADDR_S40 1
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#define PHY_ADDR_T22 2
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#define T22_TX_LEVEL_100M 0x2d
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#define T22_TX_LEVEL_10M 0x32
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static int rk630_phy_t22_get_txlevel_from_efuse(unsigned char *txlevel_100,
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unsigned char *txlevel_10)
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{
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#if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP)
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unsigned char tx_level[2];
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struct udevice *dev;
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u32 regs[2] = {0};
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ofnode node;
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int ret;
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/* retrieve the device */
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if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE))
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(rockchip_efuse),
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&dev);
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else
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(rockchip_otp),
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&dev);
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if (ret) {
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printf("%s: could not find efuse/otp device\n", __func__);
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return ret;
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}
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node = dev_read_subnode(dev, "macphy-txlevel");
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if (!ofnode_valid(node))
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return -EINVAL;
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ret = ofnode_read_u32_array(node, "reg", regs, 2);
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if (ret) {
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printf("Cannot get efuse reg\n");
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return -EINVAL;
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}
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/* read the txlevel from the efuses */
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ret = misc_read(dev, regs[0], &tx_level, 2);
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if (ret) {
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printf("%s: read txlevel from efuse/otp failed, ret=%d\n",
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__func__, ret);
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return ret;
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}
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*txlevel_100 = tx_level[1];
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*txlevel_10 = tx_level[0];
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return 0;
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#else
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return -EINVAL;
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#endif
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}
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static int rk630_phy_startup(struct phy_device *phydev)
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{
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int ret;
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/* Read the Status (2x to make sure link is right) */
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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/* Read the Status (2x to make sure link is right) */
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phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
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return genphy_parse_link(phydev);
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}
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static void rk630_phy_s40_config_init(struct phy_device *phydev)
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{
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phy_write(phydev, 0, MDIO_DEVAD_NONE,
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phy_read(phydev, MDIO_DEVAD_NONE, 0) & ~BIT(13));
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/* Switch to page 1 */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0100);
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/* Disable APS */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE1_APS_CTRL, 0x4824);
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/* Switch to page 2 */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0200);
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/* PHYAFE TRX optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE2_AFE_CTRL, 0x0000);
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/* Switch to page 6 */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0600);
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/* PHYAFE TX optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_TX_CTRL, 0x708f);
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/* PHYAFE RX optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_RX_CTRL, 0xf000);
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_DRIVER2, 0x1530);
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/* Switch to page 8 */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0800);
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/* PHYAFE TRX optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE8_AFE_CTRL, 0x00bc);
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/* Switch to page 0 */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0000);
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}
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static void rk630_phy_t22_config_init(struct phy_device *phydev)
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{
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unsigned char tx_level_100M = T22_TX_LEVEL_100M;
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unsigned char tx_level_10M = T22_TX_LEVEL_10M;
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/* Switch to page 1 */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0100);
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/* Disable APS */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE1_APS_CTRL, 0x4824);
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/* Switch to page 2 */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0200);
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/* PHYAFE TRX optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE2_AFE_CTRL, 0x0000);
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/* Switch to page 6 */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0600);
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/* PHYAFE ADC optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_ADC_ANONTROL, 0x5540);
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/* PHYAFE Gain optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_GAIN_ANONTROL, 0x0400);
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/* PHYAFE EQ optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_TX_CTRL, 0x1088);
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if (rk630_phy_t22_get_txlevel_from_efuse(&tx_level_100M, &tx_level_10M)) {
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tx_level_100M = T22_TX_LEVEL_100M;
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tx_level_10M = T22_TX_LEVEL_10M;
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}
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/* PHYAFE TX optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_DRIVER2,
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(tx_level_100M << 8) | tx_level_10M);
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/* PHYAFE CP current optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_CP_CURRENT, 0x0575);
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/* ADC OP BIAS optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_ADC_OP_BIAS, 0x0000);
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/* Rx signal detctor level optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_RX_DECTOR, 0x0408);
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/* PHYAFE PDCW optimization */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_PDCW, 0x8880);
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/* Add PHY Tx mos drive, reduce power noise/jitter */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_TX_MOS_DRV, 0x888e);
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/* Switch to page 8 */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0800);
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/* Disable auto-cal */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE8_AUTO_CAL, 0x0844);
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/* Switch to page 0 */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0000);
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/* Disable eee mode advertised */
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phy_write(phydev, MDIO_DEVAD_NONE, REG_MMD_ACCESS_CONTROL, 0x0007);
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phy_write(phydev, MDIO_DEVAD_NONE, REG_MMD_ACCESS_DATA_ADDRESS, 0x003c);
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phy_write(phydev, MDIO_DEVAD_NONE, REG_MMD_ACCESS_CONTROL, 0x4007);
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phy_write(phydev, MDIO_DEVAD_NONE, REG_MMD_ACCESS_DATA_ADDRESS, 0x0000);
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}
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static int rk630_phy_config_init(struct phy_device *phydev)
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{
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switch (phydev->addr) {
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case PHY_ADDR_S40:
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rk630_phy_s40_config_init(phydev);
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break;
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case PHY_ADDR_T22:
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rk630_phy_t22_config_init(phydev);
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break;
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default:
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printf("Unsupported address for current phy: %d\n",
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phydev->addr);
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return -EINVAL;
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}
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genphy_config_aneg(phydev);
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return 0;
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}
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static struct phy_driver RK630_driver = {
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.name = "Rockchip RK630",
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.uid = RK630_PHY_ID,
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.mask = 0xffffff,
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.features = PHY_BASIC_FEATURES,
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.config = &rk630_phy_config_init,
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.startup = &rk630_phy_startup,
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};
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int phy_rk630_init(void)
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{
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phy_register(&RK630_driver);
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return 0;
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}
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