/*
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* Davicom PHY drivers
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* author Andy Fleming
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*/
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#include <phy.h>
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#define MIIM_DM9161_SCR 0x10
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#define MIIM_DM9161_SCR_INIT 0x0610
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/* DM9161 Specified Configuration and Status Register */
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#define MIIM_DM9161_SCSR 0x11
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#define MIIM_DM9161_SCSR_100F 0x8000
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#define MIIM_DM9161_SCSR_100H 0x4000
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#define MIIM_DM9161_SCSR_10F 0x2000
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#define MIIM_DM9161_SCSR_10H 0x1000
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/* DM9161 10BT Configuration/Status */
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#define MIIM_DM9161_10BTCSR 0x12
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#define MIIM_DM9161_10BTCSR_INIT 0x7800
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/* Davicom DM9161E */
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static int dm9161_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE);
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/* Do not bypass the scrambler/descrambler */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR,
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MIIM_DM9161_SCR_INIT);
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/* Clear 10BTCSR to default */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR,
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MIIM_DM9161_10BTCSR_INIT);
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genphy_config_aneg(phydev);
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return 0;
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}
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static int dm9161_parse_status(struct phy_device *phydev)
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{
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int mii_reg;
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR);
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if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
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phydev->speed = SPEED_100;
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else
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phydev->speed = SPEED_10;
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if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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return 0;
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}
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static int dm9161_startup(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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return dm9161_parse_status(phydev);
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}
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static struct phy_driver DM9161_driver = {
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.name = "Davicom DM9161E",
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.uid = 0x181b880,
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.mask = 0xffffff0,
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.features = PHY_BASIC_FEATURES,
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.config = &dm9161_config,
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.startup = &dm9161_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_davicom_init(void)
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{
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phy_register(&DM9161_driver);
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return 0;
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}
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