/*
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* (X) extracted from enc28j60.c
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* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _enc28j60_h
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#define _enc28j60_h
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/*
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* SPI Commands
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*
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* Bits 7-5: Command
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* Bits 4-0: Register
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*/
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#define CMD_RCR(x) (0x00+((x)&0x1f)) /* Read Control Register */
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#define CMD_RBM 0x3a /* Read Buffer Memory */
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#define CMD_WCR(x) (0x40+((x)&0x1f)) /* Write Control Register */
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#define CMD_WBM 0x7a /* Write Buffer Memory */
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#define CMD_BFS(x) (0x80+((x)&0x1f)) /* Bit Field Set */
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#define CMD_BFC(x) (0xa0+((x)&0x1f)) /* Bit Field Clear */
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#define CMD_SRC 0xff /* System Reset Command */
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/* NEW: encode (bank number+1) in upper byte */
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/* Common Control Registers accessible in all Banks */
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#define CTL_REG_EIE 0x01B
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#define CTL_REG_EIR 0x01C
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#define CTL_REG_ESTAT 0x01D
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#define CTL_REG_ECON2 0x01E
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#define CTL_REG_ECON1 0x01F
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/* Control Registers accessible in Bank 0 */
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#define CTL_REG_ERDPTL 0x100
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#define CTL_REG_ERDPTH 0x101
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#define CTL_REG_EWRPTL 0x102
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#define CTL_REG_EWRPTH 0x103
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#define CTL_REG_ETXSTL 0x104
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#define CTL_REG_ETXSTH 0x105
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#define CTL_REG_ETXNDL 0x106
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#define CTL_REG_ETXNDH 0x107
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#define CTL_REG_ERXSTL 0x108
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#define CTL_REG_ERXSTH 0x109
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#define CTL_REG_ERXNDL 0x10A
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#define CTL_REG_ERXNDH 0x10B
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#define CTL_REG_ERXRDPTL 0x10C
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#define CTL_REG_ERXRDPTH 0x10D
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#define CTL_REG_ERXWRPTL 0x10E
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#define CTL_REG_ERXWRPTH 0x10F
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#define CTL_REG_EDMASTL 0x110
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#define CTL_REG_EDMASTH 0x111
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#define CTL_REG_EDMANDL 0x112
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#define CTL_REG_EDMANDH 0x113
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#define CTL_REG_EDMADSTL 0x114
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#define CTL_REG_EDMADSTH 0x115
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#define CTL_REG_EDMACSL 0x116
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#define CTL_REG_EDMACSH 0x117
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/* Control Registers accessible in Bank 1 */
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#define CTL_REG_EHT0 0x200
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#define CTL_REG_EHT1 0x201
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#define CTL_REG_EHT2 0x202
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#define CTL_REG_EHT3 0x203
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#define CTL_REG_EHT4 0x204
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#define CTL_REG_EHT5 0x205
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#define CTL_REG_EHT6 0x206
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#define CTL_REG_EHT7 0x207
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#define CTL_REG_EPMM0 0x208
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#define CTL_REG_EPMM1 0x209
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#define CTL_REG_EPMM2 0x20A
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#define CTL_REG_EPMM3 0x20B
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#define CTL_REG_EPMM4 0x20C
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#define CTL_REG_EPMM5 0x20D
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#define CTL_REG_EPMM6 0x20E
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#define CTL_REG_EPMM7 0x20F
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#define CTL_REG_EPMCSL 0x210
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#define CTL_REG_EPMCSH 0x211
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#define CTL_REG_EPMOL 0x214
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#define CTL_REG_EPMOH 0x215
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#define CTL_REG_EWOLIE 0x216
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#define CTL_REG_EWOLIR 0x217
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#define CTL_REG_ERXFCON 0x218
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#define CTL_REG_EPKTCNT 0x219
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/* Control Registers accessible in Bank 2 */
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#define CTL_REG_MACON1 0x300
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#define CTL_REG_MACON2 0x301
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#define CTL_REG_MACON3 0x302
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#define CTL_REG_MACON4 0x303
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#define CTL_REG_MABBIPG 0x304
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#define CTL_REG_MAIPGL 0x306
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#define CTL_REG_MAIPGH 0x307
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#define CTL_REG_MACLCON1 0x308
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#define CTL_REG_MACLCON2 0x309
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#define CTL_REG_MAMXFLL 0x30A
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#define CTL_REG_MAMXFLH 0x30B
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#define CTL_REG_MAPHSUP 0x30D
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#define CTL_REG_MICON 0x311
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#define CTL_REG_MICMD 0x312
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#define CTL_REG_MIREGADR 0x314
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#define CTL_REG_MIWRL 0x316
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#define CTL_REG_MIWRH 0x317
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#define CTL_REG_MIRDL 0x318
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#define CTL_REG_MIRDH 0x319
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/* Control Registers accessible in Bank 3 */
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#define CTL_REG_MAADR1 0x400
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#define CTL_REG_MAADR0 0x401
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#define CTL_REG_MAADR3 0x402
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#define CTL_REG_MAADR2 0x403
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#define CTL_REG_MAADR5 0x404
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#define CTL_REG_MAADR4 0x405
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#define CTL_REG_EBSTSD 0x406
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#define CTL_REG_EBSTCON 0x407
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#define CTL_REG_EBSTCSL 0x408
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#define CTL_REG_EBSTCSH 0x409
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#define CTL_REG_MISTAT 0x40A
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#define CTL_REG_EREVID 0x412
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#define CTL_REG_ECOCON 0x415
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#define CTL_REG_EFLOCON 0x417
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#define CTL_REG_EPAUSL 0x418
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#define CTL_REG_EPAUSH 0x419
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/* PHY Register */
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#define PHY_REG_PHCON1 0x00
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#define PHY_REG_PHSTAT1 0x01
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#define PHY_REG_PHID1 0x02
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#define PHY_REG_PHID2 0x03
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#define PHY_REG_PHCON2 0x10
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#define PHY_REG_PHSTAT2 0x11
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#define PHY_REG_PHLCON 0x14
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/* Receive Filter Register (ERXFCON) bits */
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#define ENC_RFR_UCEN 0x80
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#define ENC_RFR_ANDOR 0x40
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#define ENC_RFR_CRCEN 0x20
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#define ENC_RFR_PMEN 0x10
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#define ENC_RFR_MPEN 0x08
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#define ENC_RFR_HTEN 0x04
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#define ENC_RFR_MCEN 0x02
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#define ENC_RFR_BCEN 0x01
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/* ECON1 Register Bits */
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#define ENC_ECON1_TXRST 0x80
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#define ENC_ECON1_RXRST 0x40
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#define ENC_ECON1_DMAST 0x20
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#define ENC_ECON1_CSUMEN 0x10
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#define ENC_ECON1_TXRTS 0x08
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#define ENC_ECON1_RXEN 0x04
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#define ENC_ECON1_BSEL1 0x02
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#define ENC_ECON1_BSEL0 0x01
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/* ECON2 Register Bits */
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#define ENC_ECON2_AUTOINC 0x80
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#define ENC_ECON2_PKTDEC 0x40
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#define ENC_ECON2_PWRSV 0x20
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#define ENC_ECON2_VRPS 0x08
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/* EIR Register Bits */
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#define ENC_EIR_PKTIF 0x40
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#define ENC_EIR_DMAIF 0x20
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#define ENC_EIR_LINKIF 0x10
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#define ENC_EIR_TXIF 0x08
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#define ENC_EIR_WOLIF 0x04
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#define ENC_EIR_TXERIF 0x02
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#define ENC_EIR_RXERIF 0x01
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/* ESTAT Register Bits */
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#define ENC_ESTAT_INT 0x80
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#define ENC_ESTAT_LATECOL 0x10
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#define ENC_ESTAT_RXBUSY 0x04
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#define ENC_ESTAT_TXABRT 0x02
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#define ENC_ESTAT_CLKRDY 0x01
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/* EIE Register Bits */
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#define ENC_EIE_INTIE 0x80
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#define ENC_EIE_PKTIE 0x40
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#define ENC_EIE_DMAIE 0x20
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#define ENC_EIE_LINKIE 0x10
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#define ENC_EIE_TXIE 0x08
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#define ENC_EIE_WOLIE 0x04
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#define ENC_EIE_TXERIE 0x02
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#define ENC_EIE_RXERIE 0x01
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/* MACON1 Register Bits */
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#define ENC_MACON1_LOOPBK 0x10
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#define ENC_MACON1_TXPAUS 0x08
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#define ENC_MACON1_RXPAUS 0x04
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#define ENC_MACON1_PASSALL 0x02
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#define ENC_MACON1_MARXEN 0x01
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/* MACON2 Register Bits */
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#define ENC_MACON2_MARST 0x80
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#define ENC_MACON2_RNDRST 0x40
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#define ENC_MACON2_MARXRST 0x08
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#define ENC_MACON2_RFUNRST 0x04
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#define ENC_MACON2_MATXRST 0x02
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#define ENC_MACON2_TFUNRST 0x01
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/* MACON3 Register Bits */
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#define ENC_MACON3_PADCFG2 0x80
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#define ENC_MACON3_PADCFG1 0x40
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#define ENC_MACON3_PADCFG0 0x20
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#define ENC_MACON3_TXCRCEN 0x10
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#define ENC_MACON3_PHDRLEN 0x08
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#define ENC_MACON3_HFRMEN 0x04
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#define ENC_MACON3_FRMLNEN 0x02
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#define ENC_MACON3_FULDPX 0x01
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/* MACON4 Register Bits */
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#define ENC_MACON4_DEFER 0x40
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/* MICMD Register Bits */
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#define ENC_MICMD_MIISCAN 0x02
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#define ENC_MICMD_MIIRD 0x01
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/* MISTAT Register Bits */
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#define ENC_MISTAT_NVALID 0x04
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#define ENC_MISTAT_SCAN 0x02
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#define ENC_MISTAT_BUSY 0x01
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/* PHID1 and PHID2 values */
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#define ENC_PHID1_VALUE 0x0083
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#define ENC_PHID2_VALUE 0x1400
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#define ENC_PHID2_MASK 0xFC00
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/* PHCON1 values */
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#define ENC_PHCON1_PDPXMD 0x0100
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/* PHSTAT1 values */
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#define ENC_PHSTAT1_LLSTAT 0x0004
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/* PHSTAT2 values */
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#define ENC_PHSTAT2_LSTAT 0x0400
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#define ENC_PHSTAT2_DPXSTAT 0x0200
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#endif
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