/*
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* eFuse driver for Rockchip devices
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*
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* Copyright 2017, Theobroma Systems Design und Consulting GmbH
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* Written by Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <command.h>
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#include <display_options.h>
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#include <dm.h>
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#include <linux/arm-smccc.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <misc.h>
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#include <asm/arch/rockchip_smccc.h>
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#define T_CSB_P_S 0
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#define T_PGENB_P_S 0
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#define T_LOAD_P_S 0
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#define T_ADDR_P_S 0
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#define T_STROBE_P_S (0 + 110) /* 1.1us */
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#define T_CSB_P_L (0 + 110 + 1000 + 20) /* 200ns */
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#define T_PGENB_P_L (0 + 110 + 1000 + 20)
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#define T_LOAD_P_L (0 + 110 + 1000 + 20)
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#define T_ADDR_P_L (0 + 110 + 1000 + 20)
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#define T_STROBE_P_L (0 + 110 + 1000) /* 10us */
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#define T_CSB_R_S 0
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#define T_PGENB_R_S 0
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#define T_LOAD_R_S 0
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#define T_ADDR_R_S 2
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#define T_STROBE_R_S (2 + 3)
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#define T_CSB_R_L (2 + 3 + 3 + 3)
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#define T_PGENB_R_L (2 + 3 + 3 + 3)
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#define T_LOAD_R_L (2 + 3 + 3 + 3)
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#define T_ADDR_R_L (2 + 3 + 3 + 2)
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#define T_STROBE_R_L (2 + 3 + 3)
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#define T_CSB_P 0x28
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#define T_PGENB_P 0x2c
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#define T_LOAD_P 0x30
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#define T_ADDR_P 0x34
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#define T_STROBE_P 0x38
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#define T_CSB_R 0x3c
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#define T_PGENB_R 0x40
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#define T_LOAD_R 0x44
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#define T_ADDR_R 0x48
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#define T_STROBE_R 0x4c
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#define RK1808_USER_MODE BIT(0)
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#define RK1808_INT_FINISH BIT(0)
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#define RK1808_AUTO_ENB BIT(0)
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#define RK1808_AUTO_RD BIT(1)
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#define RK1808_A_SHIFT 16
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#define RK1808_A_MASK 0x3ff
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#define RK1808_NBYTES 4
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#define RK3399_A_SHIFT 16
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#define RK3399_A_MASK 0x3ff
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#define RK3399_NFUSES 32
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#define RK3399_BYTES_PER_FUSE 4
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#define RK3399_STROBSFTSEL BIT(9)
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#define RK3399_RSB BIT(7)
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#define RK3399_PD BIT(5)
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#define RK3399_PGENB BIT(3)
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#define RK3399_LOAD BIT(2)
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#define RK3399_STROBE BIT(1)
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#define RK3399_CSB BIT(0)
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#define RK3288_A_SHIFT 6
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#define RK3288_A_MASK 0x3ff
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#define RK3288_NFUSES 32
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#define RK3288_BYTES_PER_FUSE 1
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#define RK3288_PGENB BIT(3)
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#define RK3288_LOAD BIT(2)
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#define RK3288_STROBE BIT(1)
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#define RK3288_CSB BIT(0)
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#define RK3328_INT_STATUS 0x0018
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#define RK3328_DOUT 0x0020
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#define RK3328_AUTO_CTRL 0x0024
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#define RK3328_INT_FINISH BIT(0)
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#define RK3328_AUTO_ENB BIT(0)
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#define RK3328_AUTO_RD BIT(1)
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typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size);
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struct rockchip_efuse_regs {
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u32 ctrl; /* 0x00 efuse control register */
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u32 dout; /* 0x04 efuse data out register */
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u32 rf; /* 0x08 efuse redundancy bit used register */
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u32 _rsvd0;
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u32 jtag_pass; /* 0x10 JTAG password */
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u32 strobe_finish_ctrl;
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/* 0x14 efuse strobe finish control register */
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u32 int_status;/* 0x18 */
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u32 reserved; /* 0x1c */
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u32 dout2; /* 0x20 */
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u32 auto_ctrl; /* 0x24 */
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};
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struct rockchip_efuse_platdata {
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void __iomem *base;
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struct clk *clk;
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};
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static void rk1808_efuse_timing_init(void __iomem *base)
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{
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static bool init;
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if (init)
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return;
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/* enable auto mode */
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writel(readl(base) & (~RK1808_USER_MODE), base);
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/* setup efuse timing */
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writel((T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P);
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writel((T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P);
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writel((T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P);
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writel((T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P);
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writel((T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P);
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writel((T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R);
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writel((T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R);
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writel((T_LOAD_R_S << 16) | T_LOAD_R_L, base + T_LOAD_R);
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writel((T_ADDR_R_S << 16) | T_ADDR_R_L, base + T_ADDR_R);
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writel((T_STROBE_R_S << 16) | T_STROBE_R_L, base + T_STROBE_R);
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init = true;
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}
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static int rockchip_rk1808_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
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struct rockchip_efuse_regs *efuse =
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(struct rockchip_efuse_regs *)plat->base;
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unsigned int addr_start, addr_end, addr_offset, addr_len;
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u32 out_value, status;
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u8 *buffer;
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int ret = 0, i = 0;
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rk1808_efuse_timing_init(plat->base);
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addr_start = rounddown(offset, RK1808_NBYTES) / RK1808_NBYTES;
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addr_end = roundup(offset + size, RK1808_NBYTES) / RK1808_NBYTES;
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addr_offset = offset % RK1808_NBYTES;
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addr_len = addr_end - addr_start;
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buffer = calloc(1, sizeof(*buffer) * addr_len * RK1808_NBYTES);
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if (!buffer)
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return -ENOMEM;
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while (addr_len--) {
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writel(RK1808_AUTO_RD | RK1808_AUTO_ENB |
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((addr_start++ & RK1808_A_MASK) << RK1808_A_SHIFT),
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&efuse->auto_ctrl);
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udelay(2);
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status = readl(&efuse->int_status);
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if (!(status & RK1808_INT_FINISH)) {
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ret = -EIO;
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goto err;
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}
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out_value = readl(&efuse->dout2);
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writel(RK1808_INT_FINISH, &efuse->int_status);
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memcpy(&buffer[i], &out_value, RK1808_NBYTES);
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i += RK1808_NBYTES;
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}
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memcpy(buf, buffer + addr_offset, size);
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err:
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kfree(buffer);
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return ret;
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}
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#ifndef CONFIG_SPL_BUILD
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static int rockchip_rk3368_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
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struct rockchip_efuse_regs *efuse =
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(struct rockchip_efuse_regs *)plat->base;
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u8 *buffer = buf;
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struct arm_smccc_res res;
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/* Switch to read mode */
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sip_smc_secure_reg_write((ulong)&efuse->ctrl,
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RK3288_LOAD | RK3288_PGENB);
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udelay(1);
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while (size--) {
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res = sip_smc_secure_reg_read((ulong)&efuse->ctrl);
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sip_smc_secure_reg_write((ulong)&efuse->ctrl, res.a1 &
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(~(RK3288_A_MASK << RK3288_A_SHIFT)));
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/* set addr */
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res = sip_smc_secure_reg_read((ulong)&efuse->ctrl);
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sip_smc_secure_reg_write((ulong)&efuse->ctrl, res.a1 |
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((offset++ & RK3288_A_MASK) <<
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RK3288_A_SHIFT));
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udelay(1);
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/* strobe low to high */
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res = sip_smc_secure_reg_read((ulong)&efuse->ctrl);
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sip_smc_secure_reg_write((ulong)&efuse->ctrl,
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res.a1 | RK3288_STROBE);
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ndelay(60);
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/* read data */
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res = sip_smc_secure_reg_read((ulong)&efuse->dout);
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*buffer++ = res.a1;
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/* reset strobe to low */
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res = sip_smc_secure_reg_read((ulong)&efuse->ctrl);
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sip_smc_secure_reg_write((ulong)&efuse->ctrl,
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res.a1 & (~RK3288_STROBE));
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udelay(1);
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}
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/* Switch to standby mode */
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sip_smc_secure_reg_write((ulong)&efuse->ctrl,
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RK3288_PGENB | RK3288_CSB);
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return 0;
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}
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#endif
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static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
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struct rockchip_efuse_regs *efuse =
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(struct rockchip_efuse_regs *)plat->base;
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unsigned int addr_start, addr_end, addr_offset;
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u32 out_value;
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u8 bytes[RK3399_NFUSES * RK3399_BYTES_PER_FUSE];
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int i = 0;
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u32 addr;
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addr_start = offset / RK3399_BYTES_PER_FUSE;
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addr_offset = offset % RK3399_BYTES_PER_FUSE;
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addr_end = DIV_ROUND_UP(offset + size, RK3399_BYTES_PER_FUSE);
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/* cap to the size of the efuse block */
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if (addr_end > RK3399_NFUSES)
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addr_end = RK3399_NFUSES;
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writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
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&efuse->ctrl);
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udelay(1);
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for (addr = addr_start; addr < addr_end; addr++) {
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setbits_le32(&efuse->ctrl,
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RK3399_STROBE | (addr << RK3399_A_SHIFT));
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udelay(1);
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out_value = readl(&efuse->dout);
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clrbits_le32(&efuse->ctrl, RK3399_STROBE);
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udelay(1);
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memcpy(&bytes[i], &out_value, RK3399_BYTES_PER_FUSE);
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i += RK3399_BYTES_PER_FUSE;
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}
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/* Switch to standby mode */
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writel(RK3399_PD | RK3399_CSB, &efuse->ctrl);
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memcpy(buf, bytes + addr_offset, size);
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return 0;
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}
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static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
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struct rockchip_efuse_regs *efuse =
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(struct rockchip_efuse_regs *)plat->base;
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u8 *buffer = buf;
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int max_size = RK3288_NFUSES * RK3288_BYTES_PER_FUSE;
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if (size > (max_size - offset))
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size = max_size - offset;
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/* Switch to read mode */
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writel(RK3288_LOAD | RK3288_PGENB, &efuse->ctrl);
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udelay(1);
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while (size--) {
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writel(readl(&efuse->ctrl) &
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(~(RK3288_A_MASK << RK3288_A_SHIFT)),
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&efuse->ctrl);
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/* set addr */
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writel(readl(&efuse->ctrl) |
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((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
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&efuse->ctrl);
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udelay(1);
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/* strobe low to high */
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writel(readl(&efuse->ctrl) |
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RK3288_STROBE, &efuse->ctrl);
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ndelay(60);
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/* read data */
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*buffer++ = readl(&efuse->dout);
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/* reset strobe to low */
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writel(readl(&efuse->ctrl) &
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(~RK3288_STROBE), &efuse->ctrl);
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udelay(1);
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}
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/* Switch to standby mode */
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writel(RK3288_PGENB | RK3288_CSB, &efuse->ctrl);
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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static int rockchip_rk3288_efuse_secure_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
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struct rockchip_efuse_regs *efuse =
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(struct rockchip_efuse_regs *)plat->base;
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u8 *buffer = buf;
|
int max_size = RK3288_NFUSES * RK3288_BYTES_PER_FUSE;
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struct arm_smccc_res res;
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|
if (size > (max_size - offset))
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size = max_size - offset;
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/* Switch to read mode */
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sip_smc_secure_reg_write((ulong)&efuse->ctrl,
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RK3288_LOAD | RK3288_PGENB);
|
udelay(1);
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while (size--) {
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res = sip_smc_secure_reg_read((ulong)&efuse->ctrl);
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sip_smc_secure_reg_write((ulong)&efuse->ctrl, res.a1 &
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(~(RK3288_A_MASK << RK3288_A_SHIFT)));
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/* set addr */
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res = sip_smc_secure_reg_read((ulong)&efuse->ctrl);
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sip_smc_secure_reg_write((ulong)&efuse->ctrl, res.a1 |
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((offset++ & RK3288_A_MASK) <<
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RK3288_A_SHIFT));
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udelay(1);
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/* strobe low to high */
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res = sip_smc_secure_reg_read((ulong)&efuse->ctrl);
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sip_smc_secure_reg_write((ulong)&efuse->ctrl,
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res.a1 | RK3288_STROBE);
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ndelay(60);
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/* read data */
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res = sip_smc_secure_reg_read((ulong)&efuse->dout);
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*buffer++ = res.a1;
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/* reset strobe to low */
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res = sip_smc_secure_reg_read((ulong)&efuse->ctrl);
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sip_smc_secure_reg_write((ulong)&efuse->ctrl,
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res.a1 & (~RK3288_STROBE));
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udelay(1);
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}
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/* Switch to standby mode */
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sip_smc_secure_reg_write((ulong)&efuse->ctrl,
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RK3288_PGENB | RK3288_CSB);
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return 0;
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}
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#endif
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static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
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struct rockchip_efuse_regs *efuse =
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(struct rockchip_efuse_regs *)plat->base;
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unsigned int addr_start, addr_end, addr_offset, addr_len;
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u32 out_value, status;
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u8 *buffer;
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int ret = 0, i = 0, j = 0;
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/* Max non-secure Byte */
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if (size > 32)
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size = 32;
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/* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
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offset += 96;
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addr_start = rounddown(offset, RK3399_BYTES_PER_FUSE) /
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RK3399_BYTES_PER_FUSE;
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addr_end = roundup(offset + size, RK3399_BYTES_PER_FUSE) /
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RK3399_BYTES_PER_FUSE;
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addr_offset = offset % RK3399_BYTES_PER_FUSE;
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addr_len = addr_end - addr_start;
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buffer = calloc(1, sizeof(*buffer) * addr_len * RK3399_BYTES_PER_FUSE);
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if (!buffer)
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return -ENOMEM;
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for (j = 0; j < addr_len; j++) {
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writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
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((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
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&efuse->auto_ctrl);
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udelay(5);
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status = readl(&efuse->int_status);
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if (!(status & RK3328_INT_FINISH)) {
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ret = -EIO;
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goto err;
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}
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out_value = readl(&efuse->dout2);
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writel(RK3328_INT_FINISH, &efuse->int_status);
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memcpy(&buffer[i], &out_value, RK3399_BYTES_PER_FUSE);
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i += RK3399_BYTES_PER_FUSE;
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}
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memcpy(buf, buffer + addr_offset, size);
|
err:
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free(buffer);
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|
return ret;
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}
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static int rockchip_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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EFUSE_READ efuse_read = NULL;
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|
efuse_read = (EFUSE_READ)dev_get_driver_data(dev);
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if (!efuse_read)
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return -ENOSYS;
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|
return (*efuse_read)(dev, offset, buf, size);
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}
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static int rockchip_efuse_capatiblity(struct udevice *dev, u32 *buf)
|
{
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*buf = device_is_compatible(dev, "rockchip,rk3288-secure-efuse") ?
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OTP_S : OTP_NS;
|
|
return 0;
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}
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|
static int rockchip_efuse_ioctl(struct udevice *dev, unsigned long request,
|
void *buf)
|
{
|
int ret = -EINVAL;
|
|
switch (request) {
|
case IOCTL_REQ_CAPABILITY:
|
ret = rockchip_efuse_capatiblity(dev, buf);
|
break;
|
}
|
|
return ret;
|
}
|
|
static const struct misc_ops rockchip_efuse_ops = {
|
.read = rockchip_efuse_read,
|
.ioctl = rockchip_efuse_ioctl,
|
};
|
|
static int rockchip_efuse_ofdata_to_platdata(struct udevice *dev)
|
{
|
struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
|
|
plat->base = dev_read_addr_ptr(dev);
|
return 0;
|
}
|
|
static const struct udevice_id rockchip_efuse_ids[] = {
|
{
|
.compatible = "rockchip,rk1808-efuse",
|
.data = (ulong)&rockchip_rk1808_efuse_read,
|
},
|
#ifndef CONFIG_SPL_BUILD
|
{
|
.compatible = "rockchip,rk3288-secure-efuse",
|
.data = (ulong)&rockchip_rk3288_efuse_secure_read,
|
},
|
#endif
|
{
|
.compatible = "rockchip,rk3066a-efuse",
|
.data = (ulong)&rockchip_rk3288_efuse_read,
|
},
|
{
|
.compatible = "rockchip,rk3188-efuse",
|
.data = (ulong)&rockchip_rk3288_efuse_read,
|
},
|
{
|
.compatible = "rockchip,rk322x-efuse",
|
.data = (ulong)&rockchip_rk3288_efuse_read,
|
},
|
{
|
.compatible = "rockchip,rk3328-efuse",
|
.data = (ulong)&rockchip_rk3328_efuse_read,
|
},
|
#ifndef CONFIG_SPL_BUILD
|
{
|
.compatible = "rockchip,rk3368-efuse",
|
.data = (ulong)&rockchip_rk3368_efuse_read,
|
},
|
#endif
|
{
|
.compatible = "rockchip,rk3399-efuse",
|
.data = (ulong)&rockchip_rk3399_efuse_read,
|
},
|
{}
|
};
|
|
U_BOOT_DRIVER(rockchip_efuse) = {
|
.name = "rockchip_efuse",
|
.id = UCLASS_MISC,
|
.of_match = rockchip_efuse_ids,
|
.ofdata_to_platdata = rockchip_efuse_ofdata_to_platdata,
|
.platdata_auto_alloc_size = sizeof(struct rockchip_efuse_platdata),
|
.ops = &rockchip_efuse_ops,
|
};
|
