/*
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* (C) Copyright 2015 Google, Inc
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*
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* (C) Copyright 2008-2020 Rockchip Electronics
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* Peter, Software Engineering, <superpeter.cai@gmail.com>.
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* Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/of_access.h>
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#include <syscon.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <dm/pinctrl.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include "../pinctrl/rockchip/pinctrl-rockchip.h"
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#define OFFSET_TO_BIT(bit) (1UL << (bit))
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#ifdef CONFIG_ROCKCHIP_GPIO_V2
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#define REG_L(R) (R##_l)
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#define REG_H(R) (R##_h)
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#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \
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((readl(REG_H(REG)) & 0xFFFF) << 16))
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#define WRITE_REG(REG, VAL) \
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{\
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writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
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writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
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}
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#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK))
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#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK))
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#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \
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(READ_REG(REG) & ~(MASK)) | (VAL))
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#else
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#define READ_REG(REG) readl(REG)
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#define WRITE_REG(REG, VAL) writel(VAL, REG)
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#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK)
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#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK)
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#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL)
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#endif
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struct rockchip_gpio_priv {
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struct rockchip_gpio_regs *regs;
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struct udevice *pinctrl;
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int bank;
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char name[2];
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};
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static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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struct rockchip_gpio_regs *regs = priv->regs;
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CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset));
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return 0;
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}
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static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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struct rockchip_gpio_regs *regs = priv->regs;
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int mask = OFFSET_TO_BIT(offset);
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CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
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SETBITS_LE32(®s->swport_ddr, mask);
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return 0;
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}
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static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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struct rockchip_gpio_regs *regs = priv->regs;
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return readl(®s->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0;
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}
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static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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struct rockchip_gpio_regs *regs = priv->regs;
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int mask = OFFSET_TO_BIT(offset);
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CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
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return 0;
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}
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static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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#ifdef CONFIG_SPL_BUILD
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return -ENODATA;
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#else
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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struct rockchip_gpio_regs *regs = priv->regs;
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bool is_output;
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int ret;
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ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
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if (ret < 0) {
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dev_err(dev, "fail to get gpio mux %d\n", ret);
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return ret;
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}
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/* If it's not 0, then it is not a GPIO */
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if (ret > 0)
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return GPIOF_FUNC;
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is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset);
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return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
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#endif
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}
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static int rockchip_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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struct rockchip_pinctrl_priv *pctrl_priv;
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struct rockchip_pin_bank *bank;
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char *end = NULL;
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int id = -1, ret;
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priv->regs = dev_read_addr_ptr(dev);
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ret = uclass_get_device_by_seq(UCLASS_PINCTRL, 0, &priv->pinctrl);
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if (ret) {
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ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
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if (ret) {
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dev_err(dev, "failed to get pinctrl device %d\n", ret);
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return ret;
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}
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}
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pctrl_priv = dev_get_priv(priv->pinctrl);
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if (!pctrl_priv) {
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dev_err(dev, "failed to get pinctrl priv\n");
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return -EINVAL;
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}
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end = strrchr(dev->name, '@');
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if (end)
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id = trailing_strtoln(dev->name, end);
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if (id < 0)
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dev_read_alias_seq(dev, &id);
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if (id < 0 || id >= pctrl_priv->ctrl->nr_banks) {
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dev_err(dev, "nr_banks=%d, bank id=%d invalid\n",
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pctrl_priv->ctrl->nr_banks, id);
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return -EINVAL;
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}
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bank = &pctrl_priv->ctrl->pin_banks[id];
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if (bank->bank_num != id) {
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dev_err(dev, "bank id mismatch with pinctrl\n");
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return -EINVAL;
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}
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priv->bank = bank->bank_num;
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uc_priv->gpio_count = bank->nr_pins;
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uc_priv->gpio_base = bank->pin_base;
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uc_priv->bank_name = bank->name;
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return 0;
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}
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static const struct dm_gpio_ops gpio_rockchip_ops = {
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.direction_input = rockchip_gpio_direction_input,
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.direction_output = rockchip_gpio_direction_output,
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.get_value = rockchip_gpio_get_value,
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.set_value = rockchip_gpio_set_value,
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.get_function = rockchip_gpio_get_function,
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};
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static const struct udevice_id rockchip_gpio_ids[] = {
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{ .compatible = "rockchip,gpio-bank" },
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{ }
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};
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U_BOOT_DRIVER(gpio_rockchip) = {
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.name = "gpio_rockchip",
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.id = UCLASS_GPIO,
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.of_match = rockchip_gpio_ids,
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.ops = &gpio_rockchip_ops,
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.priv_auto_alloc_size = sizeof(struct rockchip_gpio_priv),
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.probe = rockchip_gpio_probe,
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};
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