// SPDX-License-Identifier: GPL-2.0-only
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/*
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* NCA9539 I2C Port Expander I/O
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*
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* Copyright (C) 2023 Cody Xie <cody.xie@rock-chips.com>
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*
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#include <malloc.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <linux/bitops.h>
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#define NCA9539_REG_INPUT_PORT_BASE 0x00
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#define NCA9539_REG_INPUT_PORT0 (NCA9539_REG_INPUT_PORT_BASE + 0x0)
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#define NCA9539_REG_INPUT_PORT1 (NCA9539_REG_INPUT_PORT_BASE + 0x1)
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#define NCA9539_REG_OUTPUT_PORT_BASE 0x02
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#define NCA9539_REG_OUTPUT_PORT0 (NCA9539_REG_OUTPUT_PORT_BASE + 0x0)
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#define NCA9539_REG_OUTPUT_PORT1 (NCA9539_REG_OUTPUT_PORT_BASE + 0x1)
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#define NCA9539_REG_POLARITY_BASE 0x04
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#define NCA9539_REG_POLARITY_PORT0 (NCA9539_REG_POLARITY_BASE + 0x0)
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#define NCA9539_REG_POLARITY_PORT1 (NCA9539_REG_POLARITY_BASE + 0x1)
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#define NCA9539_REG_CONFIG_BASE 0x06
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#define NCA9539_REG_CONFIG_PORT0 (NCA9539_REG_CONFIG_BASE + 0x0)
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#define NCA9539_REG_CONFIG_PORT1 (NCA9539_REG_CONFIG_BASE + 0x1)
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#define NCA9539_BANK_SZ 8
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#define NCA9539_MAX_BANK 2
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#define NCA9539_CHIP_ADDR 0x74
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#ifndef BIT
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#define BIT(nr) (1UL << (nr))
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#endif
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struct nca9539_info {
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struct udevice *dev;
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int addr;
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unsigned int ngpio;
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};
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static int nca9539_write_reg(struct udevice *dev, int reg, u8 val)
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{
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int ret = 0;
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ret = dm_i2c_write(dev, reg, &val, 1);
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if (ret) {
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dev_err(dev, "%s error\n", __func__);
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return ret;
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}
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return 0;
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}
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static int nca9539_read_reg(struct udevice *dev, int reg, u8 *val)
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{
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int ret;
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u8 byte;
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ret = dm_i2c_read(dev, reg, &byte, 1);
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if (ret) {
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dev_err(dev, "%s error\n", __func__);
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return ret;
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}
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*val = byte;
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return 0;
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}
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static int nca9539_gpio_get_direction(struct udevice *dev, unsigned int offset)
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{
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unsigned int port = offset / NCA9539_BANK_SZ;
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unsigned int pin = offset % NCA9539_BANK_SZ;
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u8 value;
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int ret;
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dev_dbg(dev, "%s offset(%d)\n", __func__, offset);
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ret = nca9539_read_reg(dev, NCA9539_REG_CONFIG_BASE + port, &value);
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if (ret < 0) {
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dev_err(dev, "%s offset(%d) read config failed\n", __func__,
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offset);
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return ret;
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}
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if (value & BIT(pin))
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return GPIOF_INPUT;
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return GPIOF_OUTPUT;
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}
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static int nca9539_gpio_direction_input(struct udevice *dev,
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unsigned int offset)
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{
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unsigned int port = offset / NCA9539_BANK_SZ;
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unsigned int pin = offset % NCA9539_BANK_SZ;
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u8 val;
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int ret = 0;
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dev_dbg(dev, "%s offset(%d)\n", __func__, offset);
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ret = nca9539_read_reg(dev, NCA9539_REG_CONFIG_BASE + port, &val);
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if (!ret) {
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val &= ~BIT(pin);
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val |= BIT(pin);
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ret = nca9539_write_reg(dev, NCA9539_REG_CONFIG_BASE + port,
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val);
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}
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if (ret < 0) {
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dev_err(dev, "%s offset(%d) read config failed\n", __func__,
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offset);
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}
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return ret;
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}
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static int nca9539_gpio_direction_output(struct udevice *dev,
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unsigned int offset, int val)
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{
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unsigned int port = offset / NCA9539_BANK_SZ;
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unsigned int pin = offset % NCA9539_BANK_SZ;
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u8 value;
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int ret;
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dev_dbg(dev, "%s offset(%d) val(%d)\n", __func__, offset, val);
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ret = nca9539_read_reg(dev, NCA9539_REG_CONFIG_BASE + port, &value);
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if (!ret) {
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value &= ~BIT(pin);
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ret = nca9539_write_reg(dev, NCA9539_REG_CONFIG_BASE + port,
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value);
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}
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if (ret < 0) {
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dev_warn(dev, "%s offset(%d) read config failed\n", __func__,
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offset);
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}
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ret = nca9539_read_reg(dev, NCA9539_REG_OUTPUT_PORT_BASE + port,
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&value);
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if (!ret) {
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value &= ~BIT(pin);
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value |= val ? BIT(pin) : 0;
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ret = nca9539_write_reg(
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dev, NCA9539_REG_OUTPUT_PORT_BASE + port, value);
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}
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if (ret < 0) {
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dev_err(dev, "%s offset(%d) val(%d) update output failed\n",
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__func__, offset, val);
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}
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return ret;
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}
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static int nca9539_gpio_get(struct udevice *dev, unsigned int offset)
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{
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unsigned int port = offset / NCA9539_BANK_SZ;
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unsigned int pin = offset % NCA9539_BANK_SZ;
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int reg;
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u8 value;
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int ret;
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dev_dbg(dev, "%s offset(%d)\n", __func__, offset);
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ret = nca9539_read_reg(dev, NCA9539_REG_CONFIG_BASE + port, &value);
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if (ret < 0) {
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dev_err(dev, "%s offset(%d) check config failed\n", __func__,
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offset);
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return ret;
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}
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if (!(BIT(pin) & value))
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reg = NCA9539_REG_OUTPUT_PORT_BASE + port;
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else
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reg = NCA9539_REG_INPUT_PORT_BASE + port;
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ret = nca9539_read_reg(dev, reg, &value);
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if (ret < 0) {
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dev_err(dev, "%s offset(%d) read value failed\n", __func__,
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offset);
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return -EIO;
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}
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return !!(BIT(pin) & value);
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}
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static int nca9539_gpio_set(struct udevice *dev, unsigned int offset, int val)
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{
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unsigned int port = offset / NCA9539_BANK_SZ;
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unsigned int pin = offset % NCA9539_BANK_SZ;
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u8 value;
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int ret;
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dev_dbg(dev, "%s offset(%d) val(%d)\n", __func__, offset, val);
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ret = nca9539_read_reg(dev, NCA9539_REG_CONFIG_BASE + port, &value);
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if (ret < 0 || !!(BIT(pin) & value)) {
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dev_warn(dev, "%s offset(%d) val(%d) check config failed\n",
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__func__, offset, val);
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}
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ret = nca9539_read_reg(dev, NCA9539_REG_OUTPUT_PORT_BASE + port,
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&value);
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if (!ret) {
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value &= ~BIT(pin);
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value |= val ? BIT(pin) : 0;
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ret = nca9539_write_reg(
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dev, NCA9539_REG_OUTPUT_PORT_BASE + port, value);
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}
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if (ret < 0) {
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dev_err(dev, "%s offset(%d) val(%d) read input failed\n",
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__func__, offset, val);
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}
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return ret;
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}
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static int nca9539_get_function(struct udevice *dev, unsigned offset)
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{
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return nca9539_gpio_get_direction(dev, offset);
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}
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static int nca9539_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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desc->offset = args->args[0];
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desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
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return 0;
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}
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static const struct dm_gpio_ops nca9539_ops = {
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.direction_input = nca9539_gpio_direction_input,
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.direction_output = nca9539_gpio_direction_output,
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.get_value = nca9539_gpio_get,
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.set_value = nca9539_gpio_set,
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.get_function = nca9539_get_function,
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.xlate = nca9539_xlate,
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};
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static int nca9539_probe(struct udevice *dev)
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{
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struct nca9539_info *info = dev_get_platdata(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
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char name[32], *str;
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ulong driver_data;
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if (!info) {
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dev_err(dev, "platdata not ready\n");
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return -ENOMEM;
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}
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if (!chip) {
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dev_err(dev, "i2c not ready\n");
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return -ENODEV;
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}
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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info->addr = chip->chip_addr;
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#else
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info->addr = NCA9539_CHIP_ADDR;
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#endif
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driver_data = dev_get_driver_data(dev);
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info->ngpio = driver_data;
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if (info->ngpio > NCA9539_MAX_BANK * NCA9539_BANK_SZ) {
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dev_err(dev, "Max support %d pins now\n",
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NCA9539_MAX_BANK * NCA9539_BANK_SZ);
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return -EINVAL;
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}
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snprintf(name, sizeof(name), "gpio@%x_", info->addr);
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str = strdup(name);
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if (!str)
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return -ENOMEM;
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uc_priv->bank_name = str;
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uc_priv->gpio_count = info->ngpio;
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dev_dbg(dev, "%s is ready\n", str);
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return 0;
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}
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static const struct udevice_id nca9539_ids[] = {
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{
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.compatible = "novo,nca9539-gpio",
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.data = (ulong)16,
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},
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{ /* sentinel */ },
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};
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U_BOOT_DRIVER(nca9539) = {
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.name = "nca9539",
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.id = UCLASS_GPIO,
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.ops = &nca9539_ops,
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.probe = nca9539_probe,
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.platdata_auto_alloc_size = sizeof(struct nca9539_info),
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.of_match = nca9539_ids,
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};
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