/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _XOR_H
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#define _XOR_H
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#define SRAM_BASE 0x40000000
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#include "ddr3_hws_hw_training_def.h"
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#define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */
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#define MV_XOR_MAX_CHAN 4 /* total channels for all units */
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#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */
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#define MV_IS_POWER_OF_2(num) (((num) != 0) && (((num) & ((num) - 1)) == 0))
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/*
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* This structure describes address space window. Window base can be
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* 64 bit, window size up to 4GB
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*/
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struct addr_win {
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u32 base_low; /* 32bit base low */
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u32 base_high; /* 32bit base high */
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u32 size; /* 32bit size */
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};
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/* This structure describes SoC units address decode window */
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struct unit_win_info {
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struct addr_win addr_win; /* An address window */
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int enable; /* Address decode window is enabled/disabled */
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u8 attrib; /* chip select attributes */
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u8 target_id; /* Target Id of this MV_TARGET */
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};
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/*
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* This enumerator describes the type of functionality the XOR channel
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* can have while using the same data structures.
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*/
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enum xor_type {
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MV_XOR, /* XOR channel functions as XOR accelerator */
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MV_DMA, /* XOR channel functions as IDMA channel */
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MV_CRC32 /* XOR channel functions as CRC 32 calculator */
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};
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enum mv_state {
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MV_IDLE,
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MV_ACTIVE,
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MV_PAUSED,
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MV_UNDEFINED_STATE
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};
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/*
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* This enumerator describes the set of commands that can be applied on
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* an engine (e.g. IDMA, XOR). Appling a comman depends on the current
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* status (see MV_STATE enumerator)
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*
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* Start can be applied only when status is IDLE
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* Stop can be applied only when status is IDLE, ACTIVE or PAUSED
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* Pause can be applied only when status is ACTIVE
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* Restart can be applied only when status is PAUSED
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*/
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enum mv_command {
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MV_START, /* Start */
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MV_STOP, /* Stop */
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MV_PAUSE, /* Pause */
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MV_RESTART /* Restart */
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};
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enum xor_override_target {
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SRC_ADDR0, /* Source Address #0 Control */
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SRC_ADDR1, /* Source Address #1 Control */
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SRC_ADDR2, /* Source Address #2 Control */
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SRC_ADDR3, /* Source Address #3 Control */
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SRC_ADDR4, /* Source Address #4 Control */
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SRC_ADDR5, /* Source Address #5 Control */
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SRC_ADDR6, /* Source Address #6 Control */
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SRC_ADDR7, /* Source Address #7 Control */
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XOR_DST_ADDR, /* Destination Address Control */
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XOR_NEXT_DESC /* Next Descriptor Address Control */
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};
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enum mv_state mv_xor_state_get(u32 chan);
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void mv_xor_hal_init(u32 xor_chan_num);
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int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
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int mv_xor_command_set(u32 chan, enum mv_command command);
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int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num,
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int enable);
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#endif
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