/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_TRAINING_LEVELING_H_
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#define _DDR3_TRAINING_LEVELING_H_
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#define MAX_DQ_READ_LEVELING_DELAY 15
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int ddr3_tip_print_wl_supp_result(u32 dev_num);
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int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
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u32 *cs_mask);
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u32 hws_ddr3_tip_max_cs_get(void);
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#endif /* _DDR3_TRAINING_LEVELING_H_ */
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