/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_TRAINING_IP_DEF_H
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#define _DDR3_TRAINING_IP_DEF_H
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#include "silicon_if.h"
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#define PATTERN_55 0x55555555
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#define PATTERN_AA 0xaaaaaaaa
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#define PATTERN_80 0x80808080
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#define PATTERN_20 0x20202020
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#define PATTERN_01 0x01010101
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#define PATTERN_FF 0xffffffff
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#define PATTERN_00 0x00000000
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/* 16bit bus width patterns */
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#define PATTERN_55AA 0x5555aaaa
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#define PATTERN_00FF 0x0000ffff
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#define PATTERN_0080 0x00008080
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#define INVALID_VALUE 0xffffffff
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#define MAX_NUM_OF_DUNITS 32
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/*
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* length *2 = length in words of pattern, first low address,
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* second high address
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*/
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#define TEST_PATTERN_LENGTH 4
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#define KILLER_PATTERN_DQ_NUMBER 8
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#define SSO_DQ_NUMBER 4
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#define PATTERN_MAXIMUM_LENGTH 64
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#define ADLL_TX_LENGTH 64
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#define ADLL_RX_LENGTH 32
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#define PARAM_NOT_CARE 0
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#define READ_LEVELING_PHY_OFFSET 2
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#define WRITE_LEVELING_PHY_OFFSET 0
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#define MASK_ALL_BITS 0xffffffff
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#define CS_BIT_MASK 0xf
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/* DFX access */
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#define BROADCAST_ID 28
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#define MULTICAST_ID 29
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#define XSB_BASE_ADDR 0x00004000
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#define XSB_CTRL_0_REG 0x00000000
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#define XSB_CTRL_1_REG 0x00000004
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#define XSB_CMD_REG 0x00000008
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#define XSB_ADDRESS_REG 0x0000000c
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#define XSB_DATA_REG 0x00000010
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#define PIPE_ENABLE_ADDR 0x000f8000
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#define ENABLE_DDR_TUNING_ADDR 0x000f829c
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#define CLIENT_BASE_ADDR 0x00002000
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#define CLIENT_CTRL_REG 0x00000000
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#define TARGET_INT 0x1801
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#define TARGET_EXT 0x180e
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#define BYTE_EN 0
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#define CMD_READ 0
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#define CMD_WRITE 1
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#define INTERNAL_ACCESS_PORT 1
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#define EXECUTING 1
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#define ACCESS_EXT 1
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#define CS2_EXIST_BIT 2
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#define TRAINING_ID 0xf
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#define EXT_TRAINING_ID 1
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#define EXT_MODE 0x4
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#define GET_RESULT_STATE(res) (res)
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#define SET_RESULT_STATE(res, state) (res = state)
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#define _1K 0x00000400
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#define _4K 0x00001000
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#define _8K 0x00002000
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#define _16K 0x00004000
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#define _32K 0x00008000
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#define _64K 0x00010000
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#define _128K 0x00020000
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#define _256K 0x00040000
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#define _512K 0x00080000
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#define _1M 0x00100000
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#define _2M 0x00200000
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#define _4M 0x00400000
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#define _8M 0x00800000
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#define _16M 0x01000000
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#define _32M 0x02000000
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#define _64M 0x04000000
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#define _128M 0x08000000
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#define _256M 0x10000000
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#define _512M 0x20000000
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#define _1G 0x40000000
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#define _2G 0x80000000
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#define ADDR_SIZE_512MB 0x04000000
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#define ADDR_SIZE_1GB 0x08000000
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#define ADDR_SIZE_2GB 0x10000000
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#define ADDR_SIZE_4GB 0x20000000
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#define ADDR_SIZE_8GB 0x40000000
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enum hws_edge_compare {
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EDGE_PF,
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EDGE_FP,
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EDGE_FPF,
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EDGE_PFP
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};
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enum hws_control_element {
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HWS_CONTROL_ELEMENT_ADLL, /* per bit 1 edge */
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HWS_CONTROL_ELEMENT_DQ_SKEW,
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HWS_CONTROL_ELEMENT_DQS_SKEW
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};
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enum hws_search_dir {
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HWS_LOW2HIGH,
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HWS_HIGH2LOW,
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HWS_SEARCH_DIR_LIMIT
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};
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enum hws_page_size {
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PAGE_SIZE_1K,
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PAGE_SIZE_2K
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};
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enum hws_operation {
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OPERATION_READ = 0,
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OPERATION_WRITE = 1
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};
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enum hws_training_ip_stat {
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HWS_TRAINING_IP_STATUS_FAIL,
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HWS_TRAINING_IP_STATUS_SUCCESS,
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HWS_TRAINING_IP_STATUS_TIMEOUT
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};
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enum hws_ddr_cs {
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CS_SINGLE,
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CS_NON_SINGLE
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};
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enum hws_ddr_phy {
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DDR_PHY_DATA = 0,
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DDR_PHY_CONTROL = 1
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};
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enum hws_dir {
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OPER_WRITE,
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OPER_READ,
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OPER_WRITE_AND_READ
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};
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enum hws_wl_supp {
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PHASE_SHIFT,
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CLOCK_SHIFT,
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ALIGN_SHIFT
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};
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struct reg_data {
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u32 reg_addr;
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u32 reg_data;
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u32 reg_mask;
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};
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#endif /* _DDR3_TRAINING_IP_DEF_H */
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