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| /*
| * Copyright (C) Marvell International Ltd. and its affiliates
| *
| * SPDX-License-Identifier: GPL-2.0
| */
|
| #ifndef _DDR3_TRAINING_IP_DB_H_
| #define _DDR3_TRAINING_IP_DB_H_
|
| enum hws_pattern {
| PATTERN_PBS1,
| PATTERN_PBS2,
| PATTERN_RL,
| PATTERN_STATIC_PBS,
| PATTERN_KILLER_DQ0,
| PATTERN_KILLER_DQ1,
| PATTERN_KILLER_DQ2,
| PATTERN_KILLER_DQ3,
| PATTERN_KILLER_DQ4,
| PATTERN_KILLER_DQ5,
| PATTERN_KILLER_DQ6,
| PATTERN_KILLER_DQ7,
| PATTERN_PBS3,
| PATTERN_RL2,
| PATTERN_TEST,
| PATTERN_FULL_SSO0,
| PATTERN_FULL_SSO1,
| PATTERN_FULL_SSO2,
| PATTERN_FULL_SSO3,
| PATTERN_VREF,
| PATTERN_LIMIT
| };
|
| #endif /* _DDR3_TRAINING_IP_DB_H_ */
|
|
