/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_TRAINING_IP_BIST_H_
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#define _DDR3_TRAINING_IP_BIST_H_
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#include "ddr3_training_ip.h"
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enum hws_bist_operation {
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BIST_STOP = 0,
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BIST_START = 1
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};
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enum hws_stress_jump {
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STRESS_NONE = 0,
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STRESS_ENABLE = 1
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};
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enum hws_pattern_duration {
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DURATION_SINGLE = 0,
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DURATION_STOP_AT_FAIL = 1,
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DURATION_ADDRESS = 2,
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DURATION_CONT = 4
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};
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struct bist_result {
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u32 bist_error_cnt;
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u32 bist_fail_low;
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u32 bist_fail_high;
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u32 bist_last_fail_addr;
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};
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int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
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struct bist_result *pst_bist_result);
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int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
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enum hws_access_type access_type,
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u32 if_num, enum hws_dir direction,
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enum hws_stress_jump addr_stress_jump,
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enum hws_pattern_duration duration,
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enum hws_bist_operation oper_type,
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u32 offset, u32 cs_num, u32 pattern_addr_length);
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int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
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u32 cs_num);
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int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
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u32 mode);
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int ddr3_tip_print_regs(u32 dev_num);
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int ddr3_tip_reg_dump(u32 dev_num);
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int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
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u32 burst_length);
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#endif /* _DDR3_TRAINING_IP_BIST_H_ */
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