/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_TRAINING_HW_ALGO_H_
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#define _DDR3_TRAINING_HW_ALGO_H_
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int ddr3_tip_vref(u32 dev_num);
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int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id);
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int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap);
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#endif /* _DDR3_TRAINING_HW_ALGO_H_ */
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