/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_HWS_HW_TRAINING_H
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#define _DDR3_HWS_HW_TRAINING_H
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/* struct used for DLB configuration array */
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struct dlb_config {
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u32 reg_addr;
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u32 reg_data;
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};
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/* Topology update structure */
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struct topology_update_info {
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int update_ecc;
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u8 ecc;
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int update_width;
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u8 width;
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int update_ecc_pup3_mode;
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u8 ecc_pup_mode_offset;
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};
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/* Topology update defines */
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#define TOPOLOGY_UPDATE_WIDTH_16BIT 1
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#define TOPOLOGY_UPDATE_WIDTH_32BIT 0
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#define TOPOLOGY_UPDATE_WIDTH_32BIT_MASK 0xf
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#define TOPOLOGY_UPDATE_WIDTH_16BIT_MASK 0x3
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#define TOPOLOGY_UPDATE_ECC_ON 1
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#define TOPOLOGY_UPDATE_ECC_OFF 0
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#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP4 4
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#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP3 3
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/*
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* 1. L2 filter should be set at binary header to 0xd000000,
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* to avoid conflict with internal register IO.
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* 2. U-Boot modifies internal registers base to 0xf100000,
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* and than should update L2 filter accordingly to 0xf000000 (3.75 GB)
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*/
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/* temporary limit l2 filter to 3GiB (LSP issue) */
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#define L2_FILTER_FOR_MAX_MEMORY_SIZE 0xc0000000
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#define ADDRESS_FILTERING_END_REGISTER 0x8c04
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#define SUB_VERSION 0
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#endif /* _DDR3_HWS_HW_TRAINING_H */
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