// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2021, Rockchip Electronics Co., Ltd
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*
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* Rockchip SARADC driver for U-Boot
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*/
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#include <common.h>
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#include <adc.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <reset.h>
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#define SARADC2_EN_END_INT BIT(0)
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#define SARADC2_START BIT(4)
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#define SARADC2_SINGLE_MODE BIT(5)
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#define SARADC_TIMEOUT (100 * 1000)
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struct rockchip_saradc_regs {
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u32 conv_con;
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u32 t_pd_soc;
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u32 t_as_soc;
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u32 t_das_soc;
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u32 t_sel_soc;
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u32 high_comp0;
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u32 high_comp1;
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u32 high_comp2;
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u32 high_comp3;
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u32 high_comp4;
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u32 high_comp5;
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u32 reserved0044;
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u32 high_comp7;
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u32 high_comp8;
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u32 high_comp9;
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u32 high_comp10;
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u32 high_comp11;
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u32 high_comp12;
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u32 high_comp13;
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u32 high_comp14;
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u32 high_comp15;
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u32 low_comp0;
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u32 low_comp1;
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u32 low_comp2;
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u32 low_comp3;
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u32 low_comp4;
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u32 low_comp5;
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u32 low_comp6;
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u32 low_comp7;
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u32 low_comp8;
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u32 low_comp9;
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u32 low_comp10;
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u32 low_comp11;
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u32 low_comp12;
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u32 low_comp13;
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u32 low_comp14;
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u32 low_comp15;
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u32 debounce;
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u32 ht_int_en;
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u32 lt_int_en;
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u32 reserved0160[24];
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u32 mt_int_en;
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u32 end_int_en;
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u32 st_con;
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u32 status;
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u32 end_int_st;
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u32 ht_int_st;
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u32 lt_int_st;
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u32 mt_int_st;
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u32 data0;
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u32 data1;
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u32 data2;
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u32 data3;
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u32 data4;
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u32 data5;
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u32 data6;
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u32 data7;
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u32 data8;
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u32 data9;
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u32 data10;
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u32 data11;
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u32 data12;
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u32 data13;
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u32 data14;
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u32 data15;
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u32 auto_ch_en;
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};
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struct rockchip_saradc_data {
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int num_bits;
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int num_channels;
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unsigned long clk_rate;
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};
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struct rockchip_saradc_priv {
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struct rockchip_saradc_regs *regs;
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int active_channel;
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const struct rockchip_saradc_data *data;
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struct reset_ctl rst;
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};
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static int rockchip_saradc_channel_data(struct udevice *dev, int channel,
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unsigned int *data)
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{
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struct rockchip_saradc_priv *priv = dev_get_priv(dev);
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struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
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if (channel != priv->active_channel) {
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pr_err("Requested channel is not active!");
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return -EINVAL;
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}
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/* Clear irq */
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writel(0x1, &priv->regs->end_int_st);
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*data = readl(&priv->regs->data0 + priv->active_channel);
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*data &= uc_pdata->data_mask;
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return 0;
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}
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static int rockchip_saradc_start_channel(struct udevice *dev, int channel)
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{
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struct rockchip_saradc_priv *priv = dev_get_priv(dev);
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int val;
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if (channel < 0 || channel >= priv->data->num_channels) {
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pr_err("Requested channel is invalid!");
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return -EINVAL;
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}
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#if CONFIG_IS_ENABLED(DM_RESET)
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reset_assert(&priv->rst);
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udelay(10);
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reset_deassert(&priv->rst);
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#endif
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writel(0x20, &priv->regs->t_pd_soc);
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writel(0xc, &priv->regs->t_das_soc);
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val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT;
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writel(val, &priv->regs->end_int_en);
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val = SARADC2_START | SARADC2_SINGLE_MODE | channel;
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writel(val << 16 | val, &priv->regs->conv_con);
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udelay(100);
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priv->active_channel = channel;
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return 0;
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}
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static int rockchip_saradc_stop(struct udevice *dev)
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{
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struct rockchip_saradc_priv *priv = dev_get_priv(dev);
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priv->active_channel = -1;
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return 0;
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}
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static int rockchip_saradc_probe(struct udevice *dev)
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{
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struct rockchip_saradc_priv *priv = dev_get_priv(dev);
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struct clk clk;
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int ret;
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#if CONFIG_IS_ENABLED(DM_RESET)
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ret = reset_get_by_name(dev, "saradc-apb", &priv->rst);
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if (ret) {
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debug("reset_get_by_name() failed: %d\n", ret);
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return ret;
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}
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#endif
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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ret = clk_set_rate(&clk, priv->data->clk_rate);
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if (IS_ERR_VALUE(ret))
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return ret;
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/* Wait until pll stable */
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mdelay(5);
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priv->active_channel = -1;
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return 0;
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}
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static int rockchip_saradc_ofdata_to_platdata(struct udevice *dev)
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{
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struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
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struct rockchip_saradc_priv *priv = dev_get_priv(dev);
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struct rockchip_saradc_data *data;
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data = (struct rockchip_saradc_data *)dev_get_driver_data(dev);
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priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev);
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if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) {
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pr_err("Dev: %s - can't get address!", dev->name);
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return -ENODATA;
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}
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priv->data = data;
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uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;
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uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
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uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5;
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uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1;
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return 0;
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}
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static const struct adc_ops rockchip_saradc_ops = {
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.start_channel = rockchip_saradc_start_channel,
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.channel_data = rockchip_saradc_channel_data,
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.stop = rockchip_saradc_stop,
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};
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static const struct rockchip_saradc_data rk3588_saradc_data = {
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.num_bits = 12,
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.num_channels = 8,
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.clk_rate = 1000000,
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};
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static const struct rockchip_saradc_data rk3562_saradc_data = {
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.num_bits = 10,
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.num_channels = 8,
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.clk_rate = 1000000,
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};
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static const struct rockchip_saradc_data rk1106_saradc_data = {
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.num_bits = 10,
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.num_channels = 2,
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.clk_rate = 1000000,
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};
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static const struct udevice_id rockchip_saradc_ids[] = {
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{
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.compatible = "rockchip,rk3588-saradc",
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.data = (ulong)&rk3588_saradc_data
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},
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{
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.compatible = "rockchip,rk3528-saradc",
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.data = (ulong)&rk3588_saradc_data
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},
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{
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.compatible = "rockchip,rk3562-saradc",
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.data = (ulong)&rk3562_saradc_data
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},
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{
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.compatible = "rockchip,rv1106-saradc",
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.data = (ulong)&rk1106_saradc_data
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},
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{ }
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};
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U_BOOT_DRIVER(rockchip_saradc_v2) = {
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.name = "rockchip_saradc_v2",
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.id = UCLASS_ADC,
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.of_match = rockchip_saradc_ids,
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.ops = &rockchip_saradc_ops,
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.probe = rockchip_saradc_probe,
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.ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct rockchip_saradc_priv),
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};
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