/*
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* Copyright (C) 2016 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#ifdef CONFIG_ROM_SIZE
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/ {
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binman {
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filename = "u-boot.rom";
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end-at-4gb;
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sort-by-pos;
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pad-byte = <0xff>;
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size = <CONFIG_ROM_SIZE>;
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#ifdef CONFIG_HAVE_INTEL_ME
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intel-descriptor {
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filename = CONFIG_FLASH_DESCRIPTOR_FILE;
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};
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intel-me {
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filename = CONFIG_INTEL_ME_FILE;
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};
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#endif
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#ifdef CONFIG_SPL
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u-boot-spl-with-ucode-ptr {
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pos = <CONFIG_SPL_TEXT_BASE>;
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};
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u-boot-dtb-with-ucode2 {
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type = "u-boot-dtb-with-ucode";
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};
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u-boot {
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pos = <0xfff00000>;
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};
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#else
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u-boot-with-ucode-ptr {
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pos = <CONFIG_SYS_TEXT_BASE>;
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};
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#endif
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u-boot-dtb-with-ucode {
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};
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u-boot-ucode {
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align = <16>;
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};
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#ifdef CONFIG_HAVE_MRC
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intel-mrc {
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pos = <CONFIG_X86_MRC_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_FSP
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intel-fsp {
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filename = CONFIG_FSP_FILE;
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pos = <CONFIG_FSP_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_CMC
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intel-cmc {
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filename = CONFIG_CMC_FILE;
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pos = <CONFIG_CMC_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_VGA_BIOS
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intel-vga {
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filename = CONFIG_VGA_BIOS_FILE;
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pos = <CONFIG_VGA_BIOS_ADDR>;
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};
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#endif
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#ifdef CONFIG_HAVE_REFCODE
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intel-refcode {
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pos = <CONFIG_X86_REFCODE_ADDR>;
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};
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#endif
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#ifdef CONFIG_SPL
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x86-start16-spl {
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pos = <CONFIG_SYS_X86_START16>;
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};
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#else
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x86-start16 {
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pos = <CONFIG_SYS_X86_START16>;
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};
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#endif
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};
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};
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#endif
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