/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ASM_ASID_H
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#define __ASM_ASM_ASID_H
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#include <linux/atomic.h>
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#include <linux/compiler.h>
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#include <linux/cpumask.h>
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#include <linux/percpu.h>
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#include <linux/spinlock.h>
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struct asid_info
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{
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atomic64_t generation;
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unsigned long *map;
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atomic64_t __percpu *active;
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u64 __percpu *reserved;
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u32 bits;
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/* Lock protecting the structure */
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raw_spinlock_t lock;
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/* Which CPU requires context flush on next call */
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cpumask_t flush_pending;
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/* Number of ASID allocated by context (shift value) */
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unsigned int ctxt_shift;
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/* Callback to locally flush the context. */
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void (*flush_cpu_ctxt_cb)(void);
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};
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#define NUM_ASIDS(info) (1UL << ((info)->bits))
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#define NUM_CTXT_ASIDS(info) (NUM_ASIDS(info) >> (info)->ctxt_shift)
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#define active_asid(info, cpu) *per_cpu_ptr((info)->active, cpu)
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void asid_new_context(struct asid_info *info, atomic64_t *pasid,
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unsigned int cpu, struct mm_struct *mm);
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/*
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* Check the ASID is still valid for the context. If not generate a new ASID.
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*
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* @pasid: Pointer to the current ASID batch
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* @cpu: current CPU ID. Must have been acquired throught get_cpu()
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*/
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static inline void asid_check_context(struct asid_info *info,
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atomic64_t *pasid, unsigned int cpu,
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struct mm_struct *mm)
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{
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u64 asid, old_active_asid;
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asid = atomic64_read(pasid);
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/*
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* The memory ordering here is subtle.
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* If our active_asid is non-zero and the ASID matches the current
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* generation, then we update the active_asid entry with a relaxed
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* cmpxchg. Racing with a concurrent rollover means that either:
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*
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* - We get a zero back from the cmpxchg and end up waiting on the
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* lock. Taking the lock synchronises with the rollover and so
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* we are forced to see the updated generation.
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*
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* - We get a valid ASID back from the cmpxchg, which means the
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* relaxed xchg in flush_context will treat us as reserved
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* because atomic RmWs are totally ordered for a given location.
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*/
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old_active_asid = atomic64_read(&active_asid(info, cpu));
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if (old_active_asid &&
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!((asid ^ atomic64_read(&info->generation)) >> info->bits) &&
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atomic64_cmpxchg_relaxed(&active_asid(info, cpu),
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old_active_asid, asid))
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return;
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asid_new_context(info, pasid, cpu, mm);
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}
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int asid_allocator_init(struct asid_info *info,
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u32 bits, unsigned int asid_per_ctxt,
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void (*flush_cpu_ctxt_cb)(void));
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#endif
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