// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3588s-orangepi-5.dtsi"
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#include "rk3588-linux.dtsi"
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#include "rk3588s-orangepi-5-lcd.dtsi"
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#include "rk3588s-orangepi-5-camera1.dtsi"
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#include "rk3588s-orangepi-5-camera2.dtsi"
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#include "rk3588s-orangepi-5-camera3.dtsi"
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/ {
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model = "Orange Pi 5";
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compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588";
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/delete-node/ chosen;
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vcc_3v3_sd_s0: vcc-3v3-sd-s0 {
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3_sd_s0";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
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enable-active-low;
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vin-supply = <&vcc_3v3_s3>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
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compatible = "regulator-fixed";
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regulator-name = "vcc_1v1_nldo_s3";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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vin-supply = <&vcc5v0_sys>;
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};
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vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_pcie2x1l2";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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enable-active-high;
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regulator-boot-on;
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regulator-always-on;
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gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <50000>;
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vin-supply = <&vcc5v0_sys>;
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};
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leds: gpio-leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 =<&leds_gpio>;
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status = "okay";
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led@1 {
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gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
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label = "status_led";
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linux,default-trigger = "heartbeat";
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linux,default-trigger-delay-ms = <0>;
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};
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};
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/* If hdmirx node is disabled, delete the reserved-memory node here. */
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* Reserve 256MB memory for hdmirx-controller@fdee0000 */
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cma {
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compatible = "shared-dma-pool";
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reusable;
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reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>;
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linux,cma-default;
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};
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};
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};
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&gmac1 {
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/* Use rgmii-rxid mode to disable rx delay inside Soc */
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phy-mode = "rgmii-rxid";
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clock_in_out = "output";
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snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1_miim
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&gmac1_tx_bus2
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&gmac1_rx_bus2
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&gmac1_rgmii_clk
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&gmac1_rgmii_bus>;
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tx_delay = <0x42>;
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/* rx_delay = <0x3f>; */
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phy-handle = <&rgmii_phy1>;
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status = "okay";
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};
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&mdio1 {
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rgmii_phy1: phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x1>;
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};
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};
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&hdmi0 {
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enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
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cec-enable;
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status = "okay";
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};
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&hdmi0_in_vp0 {
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status = "okay";
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};
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&hdmi0_sound {
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status = "okay";
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};
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&hdptxphy_hdmi0 {
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status = "okay";
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};
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&route_hdmi0{
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status = "okay";
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};
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&i2s5_8ch {
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status = "okay";
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};
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&i2s1_8ch {
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status = "okay";
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rockchip,i2s-tx-route = <3 2 1 0>;
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rockchip,i2s-rx-route = <1 3 2 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s1m0_sclk
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&i2s1m0_lrck
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&i2s1m0_sdi1
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&i2s1m0_sdo3>;
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};
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&i2c0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0m2_xfer>;
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vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
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compatible = "rockchip,rk8602";
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reg = <0x42>;
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vin-supply = <&vcc5v0_sys>;
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regulator-compatible = "rk860x-reg";
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regulator-name = "vdd_cpu_big0_s0";
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regulator-min-microvolt = <550000>;
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regulator-max-microvolt = <1050000>;
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regulator-ramp-delay = <2300>;
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rockchip,suspend-voltage-selector = <1>;
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regulator-boot-on;
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regulator-always-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
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compatible = "rockchip,rk8603";
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reg = <0x43>;
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vin-supply = <&vcc5v0_sys>;
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regulator-compatible = "rk860x-reg";
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regulator-name = "vdd_cpu_big1_s0";
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regulator-min-microvolt = <550000>;
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regulator-max-microvolt = <1050000>;
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regulator-ramp-delay = <2300>;
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rockchip,suspend-voltage-selector = <1>;
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regulator-boot-on;
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regulator-always-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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&i2c2 {
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status = "okay";
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vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
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compatible = "rockchip,rk8602";
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reg = <0x42>;
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vin-supply = <&vcc5v0_sys>;
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regulator-compatible = "rk860x-reg";
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regulator-name = "vdd_npu_s0";
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regulator-min-microvolt = <550000>;
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regulator-max-microvolt = <950000>;
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regulator-ramp-delay = <2300>;
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rockchip,suspend-voltage-selector = <1>;
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regulator-boot-on;
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regulator-always-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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/*
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pin3: GPIO1_B7
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pin5: GPIO1_B6
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*/
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&i2c5 {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5m3_xfer>;
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};
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&uart1 {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1m1_xfer>;
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};
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&pwm13 {
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status = "disabled";
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pinctrl-names = "active";
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pinctrl-0 = <&pwm13m2_pins>;
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};
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/*
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pin7: GPIO1_C6
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*/
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&pwm15 {
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status = "disabled";
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pinctrl-names = "active";
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pinctrl-0 = <&pwm15m2_pins>;
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};
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/*
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pin11: GPIO4_B2
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pin13: GPIO4_B3
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*/
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&pwm14 {
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status = "disabled";
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pinctrl-names = "active";
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pinctrl-0 = <&pwm14m1_pins>;
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};
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&can1 {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&can1m1_pins>;
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assigned-clocks = <&cru CLK_CAN1>;
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assigned-clock-rates = <200000000>;
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};
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/*
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pin15: GPIO0_D4
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pin12: GPIO0_D5
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*/
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&can2 {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&can2m1_pins>;
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assigned-clocks = <&cru CLK_CAN2>;
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assigned-clock-rates = <200000000>;
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};
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/*
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pin19: GPIO1_C1
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pin21: GPIO1_C0
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pin23: GPIO1_C2
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pin24: GPIO1_C4
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*/
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&spi4 {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>;
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assigned-clocks = <&cru CLK_SPI4>;
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assigned-clock-rates = <200000000>;
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num-cs = <2>;
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spi_dev@1 {
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compatible = "rockchip,spidev";
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reg = <1>;
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spi-max-frequency = <50000000>;
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};
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};
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&i2c3 {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3m0_xfer>;
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};
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&uart3 {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&uart3m0_xfer>;
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};
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&pwm3 {
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status = "disabled";
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pinctrl-names = "active";
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pinctrl-0 = <&pwm3m2_pins>;
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//pinctrl-0 = <&pwm3m0_pins>;
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};
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/*
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pin8: GPIO4_A3
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pin10: GPIO4_A4
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*/
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&uart0 {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0m2_xfer>;
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};
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/*
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pin16: GPIO1_D3
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pin18: GPIO1_D2
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*/
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&uart4 {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&uart4m0_xfer>;
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};
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&i2c1 {
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status = "disabled";
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pinctrl-names = "default";
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//pinctrl-0 = <&i2c1m4_xfer>;
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pinctrl-0 = <&i2c1m2_xfer>;
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};
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&pwm0 {
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status = "disabled";
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pinctrl-names = "active";
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pinctrl-0 = <&pwm0m1_pins>;
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};
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/*
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pin26: GPIO1_A3
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*/
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&pwm1 {
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status = "disabled";
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pinctrl-names = "active";
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//pinctrl-0 = <&pwm1m2_pins>;
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pinctrl-0 = <&pwm1m1_pins>;
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};
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/* watchdog */
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&wdt {
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status = "okay";
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};
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&sfc {
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status = "okay";
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max-freq = <100000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&fspim0_pins>;
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spi_flash: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-max-frequency = <100000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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loader@0 {
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label = "loader";
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reg = <0x0 0x1000000>;
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};
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};
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};
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};
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&mipi_dcphy0 {
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status = "okay";
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};
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&mipi_dcphy1 {
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status = "okay";
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};
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&rkcif {
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status = "okay";
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};
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&rkcif_mmu {
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status = "okay";
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};
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&rkisp0 {
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status = "okay";
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};
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&isp0_mmu {
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status = "okay";
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};
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&rkisp1 {
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status = "okay";
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};
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&isp1_mmu {
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status = "okay";
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};
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&sata0 {
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pinctrl-names = "default";
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pinctrl-0 = <&sata_reset>;
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status = "disabled";
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};
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&pcie2x1l2 {
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reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
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rockchip,skip-scan-in-resume;
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status = "okay";
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};
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