// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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/dts-v1/;
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#include "rk3588-evb3-lp5.dtsi"
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#include "rk3588-linux.dtsi"
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/ {
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model = "Rockchip RK3588 EVB3 LP5 V10 EDP Board";
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compatible = "rockchip,rk3588-evb3-lp5-v10-edp-linux", "rockchip,rk3588";
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panel-edp0 {
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compatible = "simple-panel";
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backlight = <&backlight>;
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power-supply = <&vcc3v3_lcd>;
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prepare-delay-ms = <120>;
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enable-delay-ms = <120>;
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unprepare-delay-ms = <120>;
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disable-delay-ms = <120>;
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width-mm = <129>;
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height-mm = <171>;
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panel-timing {
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clock-frequency = <200000000>;
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hactive = <1536>;
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vactive = <2048>;
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hfront-porch = <12>;
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hsync-len = <16>;
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hback-porch = <48>;
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vfront-porch = <8>;
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vsync-len = <4>;
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vback-porch = <8>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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port {
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panel_in_edp0: endpoint {
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remote-endpoint = <&edp0_out_panel>;
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};
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};
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};
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vcc3v3_lcd: vcc3v3-lcd {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_lcd";
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vin-supply = <&vcc_3v3_s0>;
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};
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};
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&backlight {
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enable-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
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};
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&dsi0 {
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status = "disabled";
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};
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&edp0 {
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force-hpd;
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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edp0_out_panel: endpoint {
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remote-endpoint = <&panel_in_edp0>;
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};
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};
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};
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};
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&edp0_in_vp2 {
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status = "okay";
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};
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>1x {
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status = "disabled";
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};
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&hdptxphy0 {
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lane-polarity-invert = <0 1 0 0>;
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status = "okay";
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};
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&i2c5 {
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clock-frequency = <400000>;
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status = "okay";
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gsl3673@40 {
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compatible = "GSL,GSL3673";
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reg = <0x40>;
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screen_max_x = <1536>;
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screen_max_y = <2048>;
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irq_gpio_number = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>;
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rst_gpio_number = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
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};
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};
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&pwm15 {
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pinctrl-0 = <&pwm15m1_pins>;
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};
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&vcc3v3_lcd_n {
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/delete-property/ gpio;
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};
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