// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3568.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Rockchip RK3568 IOTEST DDR3 V10 Board";
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compatible = "rockchip,rk3568-iotest-ddr3-v10", "rockchip,rk3568";
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chosen: chosen {
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bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,wake-irq = <0>;
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/* If enable uart uses irq instead of fiq */
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rockchip,irq-mode-enable = <1>;
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rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
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interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "okay";
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};
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test-power {
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status = "okay";
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};
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};
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&rkvdec {
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/delete-property/ vdec-supply;
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};
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&sdhci {
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bus-width = <8>;
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no-sdio;
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no-sd;
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non-removable;
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max-frequency = <200000000>;
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status = "okay";
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};
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&u2phy0_otg {
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status = "okay";
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};
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&usb2phy0 {
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status = "okay";
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};
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&usbdrd_dwc3 {
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dr_mode = "otg";
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phys = <&u2phy0_otg>;
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phy-names = "usb2-phy";
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extcon = <&usb2phy0>;
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maximum-speed = "high-speed";
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snps,dis_u2_susphy_quirk;
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status = "okay";
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};
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&usbdrd30 {
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status = "okay";
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};
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/delete-node/ &display_subsystem;
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